CY2309SXC-1H Cypress Semiconductor Corp, CY2309SXC-1H Datasheet - Page 8

• Manufacturer Part Number: CY2309SXC-1H
• Description: IC CLK ZDB 9OUT 133MHZ 16SOIC
• Manufacturer: Cypress Semiconductor Corp
• Type: Fanout Distribution, Zero Delay Bufferr

Specifications of CY2309SXC-1H

• Number Of Circuits: 1
• Package / Case: 16-SOIC (3.9mm Width)
• Pll: Yes with Bypass
• Input: LVCMOS, LVTTL
• Output: LVCMOS
• Ratio - Input:output: 1:9
• Differential - Input:output: No/No
• Frequency - Max: 133.33MHz
• Divider/multiplier: No/No
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Frequency-max: 133MHz
• Output Frequency Range: 10 MHz to 133.33 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 428-2207-5; CY2309SXC-1H

Switching Characteristics for CY2305SI-1H and CY2309SI-1H Industrial Temperature Devices
Switching Waveforms
Document Number : 38-07140 Rev. *M
Notes
t
t
t
t
t
t
t
t
t
t
t
t
Parameter
13. All parameters specified with loaded outputs.
14. Parameter is guaranteed by design and characterization. Not 100% tested in production.
1
DC
DC
3
4
5
6A
6B
7
8
J
LOCK
[13]
Output frequency
Duty cycle
Duty cycle
Rise time
Fall time
Output-to output skew
Delay, REF rising edge to
CLKOUT rising edge
Delay, REF rising edge to
CLKOUT rising edge
Device-to-device skew
Output slew rate
Cycle-to-cycle jitter
PLL lock time
[14]
[14]
Name
[14]
[14]
OUTPUT
OUTPUT
[14]
= t
= t
OUTPUT
[14]
2
2
÷ t
÷ t
[14]
1
1
[14]
[14]
[14]
[14]
t
0.8 V
3
1.4 V
30 pF load
10 pF load
Measured at 1.4 V, F
Measured at 1.4 V, F
Measured between 0.8 V and 2.0 V
Measured between 0.8 V and 2.0 V
All outputs equally loaded
Measured at V
Measured at V
CY2309 device only.
Measured at V
Measured between 0.8 V and 2.0 V using Test Circuit
#2
Measured at 66.67 MHz, loaded outputs
Stable power supply, valid clock presented on REF
pin
1.4 V
Figure 5. All Outputs Rise/Fall Time
t
5
2.0 V
Figure 6. Output-Output Skew
Figure 4. Duty Cycle Timing
t
1.4 V
2
DD
DD
DD
1.4 V
/2. Measured in PLL Bypass Mode,
/2
/2 on the CLKOUT pins of devices
Description
t
1
out
out
2.0 V
0.8 V
= 66.67 MHz
< 50 MHz
t
4
1.4 V
3.3 V
0 V
40.0
45.0
Min
10
10
–
–
–
–
1
–
1
–
–
CY2305, CY2309
50.0
50.0
Typ
85
60
–
–
–
–
5
–
–
–
133.33
±350
Max
60.0
55.0
1.50
1.50
100
250
700
200
8.7
1.0
–
Page 8 of 19
MHz
MHz
Unit
V/ns
ms
ns
ns
ps
ps
ns
ps
ps
%
%
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