MC100LVE111FN ON Semiconductor, MC100LVE111FN Datasheet

MC100LVE111FN

Manufacturer Part Number

MC100LVE111FN

Description

IC CLOCK DRIVER 1:9 DIFF 28-PLCC

Manufacturer

ON Semiconductor

Series

100LVEr

Type

Fanout Buffer (Distribution)r

Datasheet

1.MC100LVE111FNR2G.pdf (8 pages)

Specifications of MC100LVE111FN

Number Of Circuits

Ratio - Input:output

1:9

Differential - Input:output

Yes/Yes

Input

ECL, PECL

Output

ECL, PECL

Frequency - Max

1.5GHz

Voltage - Supply

3 V ~ 3.8 V

Operating Temperature

-40°C ~ 85°C

Mounting Type

Surface Mount

Package / Case

28-PLCC

Frequency-max

1.5GHz

Lead Free Status / RoHS Status

Contains lead / RoHS non-compliant

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MC100LVE111

3.3V ECL 1:9 Differential

Clock Driver

designed with clock distribution in mind. The MC100LVE111’s

function and performance are similar to the popular MC100E111, with

the added feature of low voltage operation. It accepts one signal input,

which can be either differential or single−ended if the V

used. The signal is fanned out to 9 identical differential outputs.

low skew as the key goal. Optimal design and layout serve to minimize

gate to gate skew within a device, and empirical modeling is used to

determine process control limits that ensure consistent t

distributions from lot to lot. The net result is a dependable, guaranteed

low skew device.

both sides of the differential output are terminated into 50 W, even if

only one side is being used. In most applications, all nine differential

pairs will be used and therefore terminated. In the case where fewer

than nine pairs are used, it is necessary to terminate at least the output

pairs on the same package side as the pair(s) being used on that side, in

order to maintain minimum skew. Failure to do this will result in small

degradations of propagation delay (on the order of 10−20 ps) of the

output(s) being used which, while not being catastrophic to most

designs, will mean a loss of skew margin.

operated from a positive V

LVE111 to be used for high performance clock distribution in +3.3 V

systems. Designers can take advantage of the LVE111’s performance

to distribute low skew clocks across the backplane or the board. In a

PECL environment, series or Thevenin line terminations are typically

used as they require no additional power supplies. For systems

incorporating GTL, parallel termination offers the lowest power by

taking advantage of the 1.2 V supply as a terminating voltage. For

more information on using PECL, designers should refer to

Application Note AN1406/D.

this device only. For single−ended input conditions, the unused

differential input is connected to V

and V

to 0.5 mA. When not used, V

Features

•

November, 2006 − Rev. 7

The MC100LVE111 is a low skew 1−to−9 differential driver,

The LVE111 is specifically designed, modeled and produced with

To ensure that the tight skew specification is met it is necessary that

The MC100LVE111, as with most other ECL devices, can be

The V

200 ps Part−to−Part Skew

50 ps Output−to−Output Skew

The 100 Series Contains Temperature Compensation

PECL Mode Operating Range: V

NECL Mode Operating Range: V

Internal Input Pulldown Resistors

Q Output will Default LOW with Inputs Open or at V

Pb−Free Packages are Available*

may also rebias AC coupled inputs. When used, decouple V

via a 0.01 mF capacitor and limit current sourcing or sinking

pin, an internally generated voltage supply, is available to

supply in PECL mode. This allows the

should be left open.

as a switching reference voltage.

= 0 V with V

= 3.0 V to 3.8 V with V

= −3.0 V to −3.8 V

output is

= 0 V

See detailed ordering and shipping information in the package

dimensions section on page 6 of this data sheet.

*For additional information on our Pb−Free strategy

and soldering details, please download the

ON Semiconductor

Techniques Reference Manual, SOLDERRM/D.

*For additional marking information, refer to

Application Note AND8002/D.

FN SUFFIX

CASE 776

PLCC−28

ORDERING INFORMATION

http://onsemi.com

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

Soldering

Publication Order Number:

MC100LVE111G

DIAGRAM*

MARKING

AWLYYWW

MC100LVE111/D

and

1 28

Mounting

Related parts for MC100LVE111FN

MC100LVE111FN Summary of contents

Page 1

... Application Note AND8002/D. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Techniques Reference Manual, SOLDERRM/D. Publication Order Number: MC100LVE111/D ...

Page 2

Warning: All Power Supply to guarantee proper operation. Figure 1. Pinout (Top View) and ...

Page 3

Table 2. ATTRIBUTES Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see ...

Page 4

Table 4. LVPECL DC CHARACTERISTICS Symbol Characteristic I Power Supply Current EE V Output HIGH Voltage (Note Output LOW Voltage (Note Input HIGH Voltage (Single−Ended Input LOW Voltage (Single−Ended Output ...

Page 5

Table 6. AC CHARACTERISTICS V Symbol Characteristic f Maximum Toggle Frequency max t Propagation Delay to Output PLH t IN (Differential Configuration) (Note 9) PHL sIN (Single−Ended) (Note 10) t Within−Device Skew (Note 11) skew Part−to−Part Skew (Differential Configuration) t ...

Page 6

... Application Note AND8020/D − Termination of ECL Logic Devices.) ORDERING INFORMATION Device MC100LVE111FN MC100LVE111FNG MC100LVE111FNR2 MC100LVE111FNR2G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Resource Reference of Application Notes AN1405/D AN1406/D ...

Page 7

0.010 (0.250) T L− NOTES: 1. DATUMS −L−, −M−, AND −N− DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT ...

Page 8

... Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303− ...

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