PCK2001MDB,112 NXP Semiconductors, PCK2001MDB,112 Datasheet - Page 10
![IC 1:10 CLOCK BUFFER 28SSOP](/photos/6/52/65218/568-28-ssop_sot341-1_sml.jpg)
PCK2001MDB,112
Manufacturer Part Number
PCK2001MDB,112
Description
IC 1:10 CLOCK BUFFER 28SSOP
Manufacturer
NXP Semiconductors
Type
Fanout Buffer (Distribution)r
Datasheet
1.PCK2001MDB118.pdf
(14 pages)
Specifications of PCK2001MDB,112
Package / Case
28-SSOP
Number Of Circuits
1
Ratio - Input:output
1:10
Differential - Input:output
No/No
Input
LVTTL
Output
LVTTL
Frequency - Max
150MHz
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Frequency-max
150MHz
Number Of Outputs
10
Max Input Freq
133 MHz
Propagation Delay (max)
2.5 ns
Supply Voltage (max)
3.465 V
Supply Voltage (min)
3.135 V
Maximum Power Dissipation
850 mW
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
935262449112
PCK2001MDB
PCK2001MDB
PCK2001MDB
PCK2001MDB
1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at power-on and are
1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at power-on and are
1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at power-on and are
Philips Semiconductors
SERIAL CONFIGURATION MAP
The serial bits will be read by the clock buffer in the following order:
All unused register bits (Reserved and N/A) should be desined as “Don’t Care”. It is expected that the controller will force all of these bits to a
“0” level.
All register bits labeled “Initialize to 0” must be written to zero during intialization. Failure to do so may result in a higher than normal operating
current. The controller will read back the last written value.
Byte 0: Output active/inactive register
1 = enable; 0 = disable
NOTE:
Byte 1: Output active/inactive register
1 = enable; 0 = disable
NOTE:
Byte 2: Optional register for possible future requirments
NOTE:
2000 May 17
14.318–150 MHz I
Byte 0 – Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 1 – Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 2 – Bits 7, 6, 5, 4, 3, 2, 1, 0
not expected to be configured during the normal modes of operation.
not expected to be configured during the normal modes of operation.
not expected to be configured during the normal modes of operation.
BIT
BIT
BIT
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
PIN#
PIN#
PIN#
27
26
23
22
18
—
—
—
—
—
—
—
—
11
—
—
—
—
—
—
7
6
3
2
2
C 1:10 clock buffer
BUF_OUT15
BUF_OUT14
BUF_OUT13
BUF_OUT12
BUF_OUT11
BUF_OUT10
BUF_OUT17
BUF_OUT16
BUF_OUT7
BUF_OUT6
BUF_OUT5
BUF_OUT4
BUF_OUT3
BUF_OUT2
BUF_OUT1
BUF_OUT0
BUF_OUT9
BUF_OUT8
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
NAME
NAME
NAME
10
DESCRIPTION
DESCRIPTION
DESCRIPTION
Active/Inactive
Active/Inactive
Active/Inactive
Active/Inactive
Active/Inactive
Active/Inactive
Active/Inactive
Active/Inactive
Active/Inactive
Active/Inactive
Initialize to 0
Initialize to 0
Initialize to 0
Initialize to 0
Initialize to 0
Initialize to 0
Initialize to 0
Initialize to 0
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
PCK2001M
Product specification