CY7B991-5JC Cypress Semiconductor Corp, CY7B991-5JC Datasheet - Page 2

• Manufacturer Part Number: CY7B991-5JC
• Description: IC CLK BUFF SKEW 8OUT 32PLCC
• Manufacturer: Cypress Semiconductor Corp
• Type: Buffer/Driverr
• Series: RoboClock™r

Specifications of CY7B991-5JC

• Number Of Circuits: 1
• Package / Case: 32-PLCC
• Ratio - Input:output: 8:8
• Differential - Input:output: Yes/Yes
• Input: 3-State, TTL
• Output: TTL
• Frequency - Max: 80MHz
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Frequency-max: 80MHz
• Output Frequency Range: 3.75 MHz to 80 MHz
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 5 V
• Number Of Elements: 1
• Supply Current: 85mA
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: 0C to 70C
• Package Type: PLCC
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Commercial
• Pin Count: 32
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 428-1375

Pin Definitions
Block Diagram Description
Phase Frequency Detector and Filter
These two blocks accept inputs from the reference frequency
(REF) input and the feedback (FB) input and generate correc-
tion information to control the frequency of the Voltage-Con-
trolled Oscillator (VCO). These blocks, along with the VCO,
form a Phase-Locked Loop (PLL) that tracks the incoming
REF signal.
VCO and Time Unit Generator
The VCO accepts analog control inputs from the PLL filter
block and generates a frequency that is used by the time unit
generator to create discrete time units that are selected in the
skew select matrix. The operational range of the VCO is de-
termined by the FS control pin. The time unit (t
by the operating frequency of the device and the level of the
FS pin as shown in Table 1.
Table 1. Frequency Range Select and t
Skew Select Matrix
The skew select matrix is comprised of four independent sec-
tions. Each section has two low-skew, high-fanout drivers
(xQ0, xQ1), and two corresponding three-level function select
Document #: 38-07138 Rev. **
REF
FB
FS
1F0, 1F1
2F0, 2F1
3F0, 3F1
4F0, 4F1
TEST
1Q0, 1Q1
2Q0, 2Q1
3Q0, 3Q1
4Q0, 4Q1
V
V
GND
FS
LOW
MID
HIGH
CCN
CCQ
[2, 3]
Signal
Name
f
Min. Max.
NOM
15
25
40
(MHz)
30
50
80
PWR
PWR
PWR
I/O
O
O
O
O
I
I
I
I
I
I
I
I
t
U
where N =
=
Reference frequency input. This input supplies the frequency and timing against which all functional
variation is measured.
PLL feedback input (typically connected to one of the eight outputs).
Three-level frequency range select. See Table 1.
Three-level function select inputs for output pair 1 (1Q0, 1Q1). See Table 2.
Three-level function select inputs for output pair 2 (2Q0, 2Q1). See Table 2.
Three-level function select inputs for output pair 3 (3Q0, 3Q1). See Table 2.
Three-level function select inputs for output pair 4 (4Q0, 4Q1). See Table 2.
Three-level select. See test mode section under the block diagram descriptions.
Output pair 1. See Table 2.
Output pair 2. See Table 2.
Output pair 3. See Table 2.
Output pair 4. See Table 2.
Power supply for output drivers.
Power supply for internal circuitry.
Ground.
----------------------- -
f
44
26
16
NOM
1
N
Frequency (MHz) At
Which t
U
Approximate
Calculation
U
) is determined
22.7
38.5
62.5
U
= 1.0 ns
[1]
(xF0, xF1) inputs. Table 2 below shows the nine possible out-
put functions for each section as determined by the function
select inputs. All times are measured with respect to the REF
input assuming that the output connected to the FB input has
0t
Table 2. Programmable Skew Configurations
1F1, 2F1,
LOW
LOW
LOW
MID
MID
MID
HIGH
HIGH
HIGH
Notes:
3F1, 4F1
1.
2.
3.
U
Function Selects
selected.
For all three-state inputs, HIGH indicates a connection to V
indicates a connection to GND, and MID indicates an open connection.
Internal termination circuitry holds an unconnected input to V
The level to be set on FS is determined by the “normal” operating fre-
quency (f
Diagram). Nominal frequency (f
other outputs when they are operated in their undivided modes (see
Table 2). The frequency appearing at the REF and FB inputs will be f
when the output connected to FB is undivided. The frequency of the REF
and FB inputs will be f
frequency multiplication by using a divided output as the FB input.
When the FS pin is selected HIGH, the REF input must not transition
upon power-up until V
Description
NOM
1F0, 2F0,
LOW
MID
HIGH
LOW
MID
HIGH
LOW
MID
HIGH
3F0, 4F0
) of the V
NOM
CC
CO
1Q0, 1Q1,
2Q0, 2Q1
has reached 4.3V.
and Time Unit Generator (see Logic Block
/2 or f
–4t
–3t
–2t
–1t
+1t
+2t
+3t
+4t
0t
NOM
U
NOM
U
U
U
U
U
U
U
U
) always appears at 1Q0 and the
Output Functions
/4 when the part is configured for a
Divide by 2 Divide by 2
Divide by 4
3Q0, 3Q1
–6t
–4t
–2t
+2t
+4t
+6t
0t
U
U
U
U
U
U
U
CY7B991
CY7B992
Page 2 of 15
[1]
4Q0, 4Q1
Inverted
CC
CC
–6t
–4t
–2t
+2t
+4t
+6t
, LOW
0t
/2.
U
U
U
U
U
U
U
NOM