SY898533LKZ Micrel Inc, SY898533LKZ Datasheet - Page 3

• Manufacturer Part Number: SY898533LKZ
• Description: IC BUFFER 1:4 LVPECL 20-TSSOP
• Manufacturer: Micrel Inc
• Series: Precision Edge®r
• Type: Fanout Buffer (Distribution), Multiplexerr

Specifications of SY898533LKZ

• Number Of Circuits: 1
• Ratio - Input:output: 2:4
• Differential - Input:output: Yes/Yes
• Input: CML, HCSL, LVDS, LVHSTL, LVPECL, SSTL
• Output: LVPECL
• Frequency - Max: 650MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 20-TSSOP
• Frequency-max: 650MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 576-3560-5

Micrel, Inc.
Pin Description
Truth Table
July 2009
Pin Number
10, 13, 18
CLK_EN
20, 19
17, 16
15, 14
12, 11
4, 5
6, 7
8, 9
1
2
3
0
0
1
1
PCLK, /PCLK
CLK_SEL
CLK, /CLK
Pin Name
CLK_SEL
CLK_EN
Inputs
Q0, /Q0
Q1, /Q1
Q2, /Q2
Q3, /Q3
VCC
V
0
1
0
1
NC
EE
Selected Source
PCLK, /PCLK
PCLK, /PCLK
Pin Function
Ground.
Single-Ended Input: This TTL/CMOS input disables and enables the Q0-Q3 outputs. It is
internally connected to a 50kΩ pull-up resistor and will default to a logic HIGH state if left
open. When disabled, Q goes LOW and /Q goes HIGH. CLK_EN being synchronous,
outputs will be enabled/disabled following a rising and a falling edge of the input clock.
V
Single-Ended Input: This single-ended TTL/CMOS-compatible input selects the input to
the multiplexer. Note that this input is internally connected to a 50kΩ pull-down resistor
and will default to logic LOW state if left open. V
Differential Input: This input pair is a differential signal input to the device. This input
accepts AC- or DC-coupled signals. CLK is internally connected to a 28kΩ pull-down
resistor and will default to a logic LOW state if left open while /CLK is connected to a
50kΩ pull-up resistor and will default to a logic HIGH state if left open. This input pair is
selected when CLK_SEL is set to logic LOW.
Differential Input: This input pair is a differential signal input to the device. This input
accepts AC- or DC-coupled signals. PCLK is internally connected to a 50kΩ pull-down
resistor and will default to a logic LOW state if left open while /PCLK is connected to a
50kΩ pull-up resistor and will default to a logic HIGH state if left open. This input pair is
selected when CLK_SEL is set to logic HIGH.
Unused Pins
Positive Power Supply Pins: Bypass with 0.1µF||0.01µF low ESR capacitors as close to
the V
LVPECL Differential Output Pairs: Differential buffered output copies of the selected input
signal. The output swing is typically 800mV. Unused output pairs may be left floating with
no impact on jitter. These differential LVPECL outputs are a logic function of the CLK,
/CLK and PCLK, /PCLK, and CLK_SEL inputs. See “Truth Table” below.
CLK, /CLK
CLK, /CLK
TH
= is approximately 1.5V.
CC
pins as possible.
Disabled : LOW
Disabled : LOW
Q0 :Q3
PCLK
CLK
4
Outputs
Disabled : HIGH
Disabled : HIGH
/Q0:/Q3
/PCLK
/CLK
TH
= is approximately 1.5V.
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SY898533L