SY89202UMG Micrel Inc, SY89202UMG Datasheet - Page 7

• Manufacturer Part Number: SY89202UMG
• Description: IC BUFFER/CLK DIVIDER 1:8 32-MLF
• Manufacturer: Micrel Inc
• Type: Fanout Buffer (Distribution), Divider, Multiplexerr
• Series: Precision Edge®r

Specifications of SY89202UMG

• Number Of Circuits: 1
• Ratio - Input:output: 1:8
• Differential - Input:output: Yes/Yes
• Input: CML, LVDS, PECL
• Output: LVPECL
• Frequency - Max: 1.5GHz
• Voltage - Supply: 2.375 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-MLF®, QFN
• Frequency-max: 1.5GHz
• Number Of Clock Inputs: 1
• Mode Of Operation: Differential
• Output Logic Level: LVPECL
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Package Type: MLF
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Signal Type: CML/LVDS/PECL
• Mounting: Surface Mount
• Pin Count: 32
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 576-1537-5; SY89202UMG

AC Electrical Characteristics
V
Notes:
6.
7.
8.
9.
10. Deterministic jitter is measured with a K28.7 101010 pattern, measured at <f
11. Random jitter is measured with a K28.7 101010 pattern, measured at <f
12. Total jitter definition: with an ideal clock input of frequency <f
13. Cycle-to-cycle jitter definition: the variation of periods between adjacent cycles, T
Micrel, Inc.
Symbol
f
t
t
Tempco
t
t
t
August 2007
CC
MAX
PD
PD
SKEW
JITTER
r,
t
f
Measured with 100mV input swing. See “Timing Diagrams” section for definition of parameters. High-frequency AC-parameters are guaranteed by
design and characterization.
Within-bank skew is the difference in propagation delays among the outputs within the same bank.
Bank-to-bank skew is the difference in propagation delays between outputs from different banks. Bank-to-bank skew is also the phase offset
between each bank, after MR is applied.
Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at the
respective inputs.
specified peak-to-peak jitter value.
signal.
= 2.5V ±5% or 3.3V ±10%; T
Parameter
Maximum Output Toggle Frequency
Maximum Input Frequency
Differential Propagation Delay
/MR – Q Propagation Delay
Differential Propagation Delay
Temperature Coefficient
Within-bank Skew
Bank-to-Bank Skew
Bank-to-Bank Skew
Part-to-Part Skew
Deterministic Jitter (DJ)
Random Jitter (RJ)
Total Jitter
Cycle-to-Cycle Jitter
Output Rise/Fall Time
A
= –40ºC to + 85ºC, R
(6)
Condition
Output swing ≥ 400mV
IN-to-Q
Within same fanout bank, Note 7
Same divide setting, Note 8
Different divide setting, Note 8
Note 9
Note 10
Note 11
Note 12
Note 13
20% to 80%, At full output swing.
MAX
, no more than one output edge in 10
L
= 50Ω to V
MAX
7
.
MAX
.
CC
n
–2V, unless otherwise stated.
– T
n-1
where T is the time between rising edges of the output
[e-mail]
12
Min
530
1.5
3.0
70
output edges will deviate by more than the
Typ
700
115
130
10
15
25
or [phone]
Max
M9999-083107-C
930
900
200
220
25
35
50
10
10
1
1
SY89202U
ps
ps
Units
fs/
GHz
GHz
ps
ps
ps
ps
ps
ps
ps
ps
ps
RMS
RMS
o
PP
PP
C