SY100EP15VK4G Micrel Inc, SY100EP15VK4G Datasheet - Page 3

• Manufacturer Part Number: SY100EP15VK4G
• Description: IC BUFFER FAN 1:4 3.3/5V 16TSSOP
• Manufacturer: Micrel Inc
• Type: Fanout Buffer (Distribution), Multiplexerr
• Series: 100EP, Precision Edge®, ECL Pro™r

Specifications of SY100EP15VK4G

• Number Of Circuits: 1
• Ratio - Input:output: 4:4
• Differential - Input:output: Yes/Yes
• Input: HSTL, LVECL, LVPECL
• Output: LVECL, LVPECL
• Frequency - Max: 2.5GHz
• Voltage - Supply: 2.97 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Frequency-max: 2.5GHz
• Frequency: 2.5GHz
• No. Of Outputs: 4
• Supply Current: 52mA
• Supply Voltage Range: ± 2.97V To ± 3.63V, ± 4.5V To ± 5.5V
• Digital Ic Case Style: TSSOP
• No. Of Pins: 16
• Number Of Clock Inputs: 2
• Operating Supply Voltage (min): -2.97/2.97V
• Operating Supply Voltage (typ): -3.3/-5/3.3/5V
• Operating Supply Voltage (max): -5.5/5.5V
• Package Type: TSSOP
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 576-1992-5; SY100EP15VK4G

Micrel, Inc.
Note:
1.
M9999-120505
[e-mail] or [phone]
TRUTH TABLE
1, 2, 3, 4
5, 6, 7, 8
CLK0
PIN DESCRIPTION
11, 12
H
L
X
X
X
Pin
= Negative edge.
10
13
14
15
16
9
CLK1
CLK0, /CLK0
Pin Number
X
X
H
X
L
/Q0 – /Q3
Q0 – Q3
CLK1
VCC
VEE
VBB
SEL
/EN
(1)
SEL
H
H
H
L
L
L
Outputs 0 through 3: 100KEP (LV)PECL/(LV)ECL compatible differential outputs. Terminate
with 50Ω to V
resistor to the most negative supply. Unused single-ended outputs must have a balanced load.
For AC-coupled applications, the output stage emitter follower must have a DC current path to
ground. See “Termination” section.
Negative Power Supply: For PECL/LVPECL applications, connect to GND.
100KEP (LV)PECL/(LV)ECL Compatible 2:1 Mux Input Select Control. See “Truth Table.” The
select (SEL) pin includes an internal 75kΩ pull-down resistor. Default condition when left floating
is LOW, and CLK0 input is selected.
Differential (LV)PECL/(LV)ECL/HSTL Compatible Input: The inputs include an internal 75kΩ
pull-down resistor on CLK0 and internal 75kΩ pull-up and pull-down on /CLK0. Default condition
for CLK0 is LOW when left floating and V
Reference Output Voltage: This reference is typically used to bias the unused inverting input for
single-ended input applications, or as the termination point for AC-coupled differential input
applications. V
sink/source capability for V
through a 50Ω resistor. Decouple the V
Single-Ended (LV)PECL/(LV)ECL Compatible Input: This pin includes an internal 75kΩ
pull-down resistor. Default condition is LOW when left floating.
100KEP (LV)PECL/(LV)ECL Compatible Input: This synchronous pin controls the output state.
See “Truth Table.” To ensure proper synchronous operation, adhere to the Set-up and Hold
times, as described in the AC electrical table. When /EN pin goes HIGH, Q outputs go LOW, and
/Q outputs go HIGH on the next falling clock transition. This synchronous operation avoids any
chance of generating a runt pulse.
Positive Power Supply: Bypass with 0.1µF//0.01µF low ESR capacitors.
/EN
H
H
L
L
L
L
CC
BB
–2V. Unused output pairs may be left floating, or pulled-down with a 2kΩ
reference value is approximately V
Q
H
H
L
L
L
L
BB
is 0.50mA. For single ended inputs, connect to the unused input
3
Function
BB
CC
pin with a 0.01µF capacitor to V
/2 for /CLK0 when left floating.
CC
–1.3V, and tracks Vcc 1:1. Maximum
CC
.
SY100EP15V
ECL Pro™