PCK2002PLPW,118 NXP Semiconductors, PCK2002PLPW,118 Datasheet - Page 5

• Manufacturer Part Number: PCK2002PLPW,118
• Description: IC PCI-X CLOCK BUFF 533MHZ8TSSOP
• Manufacturer: NXP Semiconductors
• Type: Fanout Buffer (Distribution)r

Specifications of PCK2002PLPW,118

• Package / Case: 8-TSSOP
• Number Of Circuits: 1
• Ratio - Input:output: 1:4
• Differential - Input:output: No/No
• Input: LVTTL
• Output: LVTTL
• Frequency - Max: 533MHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Frequency-max: 533MHz
• Number Of Outputs: 4
• Propagation Delay (max): 2.9 ns
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Power Dissipation: 850 mW
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Max Output Freq: 533 MHz
• Mounting Style: SMD/SMT
• Supply Current: 100 uA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935269971118; PCK2002PLPWDH-T; PCK2002PLPWDH-T

1. CLK skew is only valid for equal loading of all outputs.
2. T
3. T
4. T
5. Input edge rate for these tests must be faster than 1 V/ns.
6. All typical values are at V
Philips Semiconductors
AC CHARACTERISTICS
NOTES:
AC WAVEFORMS
V
C
V
output load.
2002 Oct 10
M
OL
L
533 MHz PCI-X clock buffer
= 10 pF
SYMBOL
= 50% V
T
and V
H
L
R
BUF_OUT
T
DDSKW
T
T
is measured at 0.35 V
is measured at 0.5 V
and T
T
T
T
SKW
T
T
T
PLH
PHL
BUF_IN
0.35 V
H
H
R
F
INPUT
L
L
0.5 V
0.4 V
OH
Figure 1. Load circuitry for switching times.
DD
F
DD
DD
DD
are the typical output voltage drop that occur with the
are measured as a transition through the threshold region 0.2 V
0.6 V
0.2 V
Figure 2. Buffer Output clock
CLK HIGH time
CLK LOW time
CLK HIGH time
CLK LOW time
Output rise slew rate
Output fall slew rate
Buffer LH propagation delay
Buffer HL propagation delay
Bus CLK skew
Device to device skew
DD
DD
V
T
M
t
R
t
PLH
DD
h
DD
CC
V
M
as shown in Figure 2.
PARAMETER
as shown in Figure 2.
= 3.3 V and T
t
p
V
M
V
t
l
DD
t
PHL
amb
= 25 C.
SW00812
V
M
T
F
SW00811
0.6 V
0.2 V
DD
DD
TEST CONDITIONS
140 MHz
140 MHz
66 MHz
66 MHz
5
TEST CIRCUIT
DD
to 0.6 V
GENERATOR
NOTES
PULSE
2
3
2
3
4
4
5
5
1
1
Figure 3. Load circuitry for switching times
DD
and 0.6 V
MIN
2.15
6.0
6.0
2.9
3.0
2.5
1.8
1.8
—
—
V
I
R
T
T
amb
DD
to 0.2 V
= –40 to +85 C
LIMITS
D.U.T.
TYP
V
3.3
3.3
2.9
2.8
DD
—
—
—
—
—
—
DD
6
.
V
O
PCK2002PL
C
L
MAX
200
500
4.1
4.4
3.4
3.4
—
—
—
—
V
SW00813
DD
Product data
140
140
UNIT
V/ns
V/ns
ns
ns
ns
ns
ns
ns
ps
ps