SI5023-D-GM Silicon Laboratories Inc, SI5023-D-GM Datasheet
SI5023-D-GM
Specifications of SI5023-D-GM
Related parts for SI5023-D-GM
SI5023-D-GM Summary of contents
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... PLL less susceptible to board-level interaction and helping to ensure optimal jitter performance. The Si5023 represents a new standard in low jitter, low power, small size, and integration for high-speed LA/CDRs. It operates from a 3.3 V supply over the industrial temperature range (– °C). ...
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... Si5023 2 Rev. 1.3 ...
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... Data Squelch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.15. Device Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.16. Bias Generation Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.17. Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.18. Differential Input Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.19. Differential Output Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5. Pin Descriptions: Si5023 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7. Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 8. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Rev. 1.3 ...
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... Si5023 1. Detailed Block Diagram LOS BER_LVL Signal LOS_LVL Detect DIN+ Limiting Phase Amp Detector DIN+ Slicing SLICE_LVL Control REFCLK± (optional) Bias REXT Generation 4 RATESEL[0:1] BER_ALM BERMON LTR BER Monitor A/D DSP VCO n Lock Detection Calibration Rev. 1.3 DSQLCH DOUT+ Retime DOUT– ...
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... All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise stated. 2. The Si5023 specifications are guaranteed when using the recommended application circuit (including component tolerance) of "3. Typical Application Schematic" on page 11. ...
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... Si5023 DO UT, CLKO UT Figure 3. DOUT and CLKOUT Rise/Fall Times RESET/Cal LOL DATAIN LOL DATAIN LOS Figure 4. PLL Acquisition Time t LOS Figure 5. LOS Response Time Rev. 1.3 80% 20% LOS Threshold Level ...
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... V OD Line-to-Line 100 Ω Load V OCM Line-to-Line R Single-ended OUT Rev. 1.3 Si5023 Min Typ Max Unit — 173 184 mA — 170 180 — 175 185 — 180 190 — 190 197 — 571 637 mW ) — 561 623 — 577 640 — ...
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... Si5023 Table 3. AC Characteristics (Clock and Data 3.3 V ±5 – ° Parameter Output Clock Rate Output Clock Rise Time—OC-48 Output Clock Fall Time—OC-48 Output Clock Duty Cycle OC-48/12/3 Output Data Rise Time—OC-48 Output Data Fall Time—OC-48 Clock-to-Data Delay FEC (2 ...
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... OC-3 Mode After falling edge of AQ RESET/CAL From the return of valid data T After falling edge of AQ RESET/CAL From the return of valid data See Table 8 on page 13 C TOL Rev. 1.3 Si5023 Min Typ Max Unit 40 — — — — — — ...
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... Si5023 Table 5. Absolute Maximum Ratings Parameter DC Supply Voltage LVTTL Input Voltage Differential Input Voltages Maximum Current any output PIN Operating Junction Temperature Storage Temperature Range ESD HBM Tolerance (100 pf, 1.5 kΩ) Note: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operational sections of this data sheet ...
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... BER Alarm LVTTL Loss-of-Signal Indicator Indicator Loss-of-Lock Indicator 2 DOUT+ DOUT– Si5023 CLKOUT+ CLKOUT– 100 pF x (4) VDD 10 k Ω 0.1 mF (1%) Data Slice Level Set Level Set Rev. 1.3 Si5023 BER Monitor 5 kW (Optional. See Table 9) Recovered Data Recovered Clock 11 ...
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... DSPLL The Si5023 PLL structure (shown in Figure 1 on page 5) utilizes Silicon Laboratories' DSPLL technology to maintain superior jitter performance while eliminating the need for external loop filter components found in traditional PLL implementations. This is achieved by ...
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... DSPLL, minimizes the acquisition time, and maintains a stable output clock (CLKOUT) when lock- to-reference (LTR) is asserted. When the reference clock is present, the Si5023 will use the reference clock to center the VCO output frequency so that clock and data can be recovered from the input data stream ...
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... SONET/SDH equipment by Bellcore GR-253-CORE, Issue 3, September 2000 and ITU-T G.958. LOS Alarm 4.11.1. Jitter Tolerance The Si5023’s tolerance to input jitter exceeds that of the Bellcore/ITU mask shown in Figure 14. This mask defines the level of peak-to-peak sinusoidal jitter that must be tolerated when applied to the differential data input of the device ...
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... Range of Operation -0.100 1.E-07 1.E-08 1.E-09 Note: For Bit Error Rate < 1.E-09, BERMON (V) is < 0.4 V. Figure 8. Si5023 OC-48 BERMON Voltage Characteristics 0.900 0.800 0.700 0.600 0.500 0.400 0.300 0.200 0.100 0.000 Range of Operation -0.100 1 ...
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... Note: For Bit Error Rate < 1.E-09, BERMON (V) is < 0.3 V. Figure 10. Si5023 OC-12/OC-3 BERMON Voltage Characteristics 6.8 μF Si5023 CDR 13.7 kΩ BERMO N 5 kΩ 1% *Note: See Table 9 (Si5023 Pin Descriptions) Figure 11. Si5023 BERMON Application Schematic 16 Range of Operation 1.E-04 1.E-06 1.E-05 Bit Error Rate 1Hz LPF 13.7 kΩ ...
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... Note: SLICE is a continuous curve. This chart shows the range of results from part-to-part. 0.75 1.00 1.25 1. Upper Limit Typical Note: SLICE is a continuous curve. This chart shows the range of results from part-to-part. Lower Limit 0.75 1.00 1.25 1.50 Rev. 1.3 Si5023 10 mV 1.75 2.00 2. 1.75 2.00 2.25 17 ...
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... Slope 4.15. Device Grounding The Si5023 uses the GND pad on the bottom of the 28- lead micro leaded package (QFN) for device ground. This pad should be connected directly to the analog supply ground. See Figure 21 on page 22 and Figure 22 on page 26 for the ground (GND) pad size and location. ...
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... Voltage Regulator The Si5023 regulates 2.5 V internally down from the external 3.3 V supply. Consumption is typically 170 mA. The Si5023 may accept control inputs as high as 3.6 V. 4.18. Differential Input Circuitry The Si5023 provides differential inputs for both the high-speed data (DIN) and the reference clock (REFCLK) inputs. Example terminations for these inputs are shown in Figures 16, 17, 18, and 19. In applications where direct dc coupling is possible, the 0.1 μ ...
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... Si5023 Clock source 0.1 μF Figure 18. Single-Ended Input Termination for REFCLK (ac coupled) Signal source 0.1 μF Figure 19. Single-Ended Input Termination for DIN (ac coupled) 20 2.5 V (±5%) 2.5 kΩ Ω RFCLK + 10 kΩ 2.5 kΩ 50 Ω RFCLK – 10 kΩ 0.1 μF GND Ω ...
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... Differential Output Circuitry The Si5023 utilizes a CML architecture to output both the recovered clock (CLKOUT) and data (DOUT). An example of output termination with ac coupling is shown in Figure 20. In applications in which direct dc coupling is possible, the 0.1 µF capacitors may be omitted. The differential peak-to-peak voltage swing of the CML architecture is specified in Table 2. 2.5 V (± ...
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... Top View Figure 21. Si5023 Pin Configuration Table 9. Si5023 Pin Descriptions I/O Signal Level I LVTTL Data Rate Select. These pins configure the onboard PLL for clock and data recovery at one of four user selectable data rates. See Table 7 for configuration settings. Notes: 1. These inputs have weak internal pullups. ...
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... Table 9. Si5023 Pin Descriptions (Continued) Pin # Pin Name 5 REFCLK+ 6 REFCLK– 7 LOL 8 LTR 9 LOS 10 DSQLCH 11,14,18,21, VDD 25 12 DIN+ 13 DIN– 15 GND 16 DOUT– 17 DOUT+ I/O Signal Level I See Table 2 Differential Reference Clock (Optional). When present, the reference clock sets the center operating frequency of the DSPLL for clock and data recovery. Tie REFCLK+ to VDD and REFCLK– ...
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... Si5023 Table 9. Si5023 Pin Descriptions (Continued) Pin # Pin Name 19 RESET/CAL 20 REXT 22 CLKOUT– 23 CLKOUT+ 24 CLKDSBL 26 BER_LVL 27 BER_ALM 28 BERMON GND Pad GND 24 I/O Signal Level I LVTTL Reset/Calibrate. Driving this input high for at least 1 μs will reset internal device circuitry. A high to low transition on this pin will force a DSPLL calibration ...
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... These devices use a NiPdAu pre-plated finish on the leads that is fully RoHS6 compliant while being fully compatible with both leaded and lead-free card assembly processes. 7. Top Mark Part Number Si5023 Voltage Pb-Free 3.3 Yes Die Revision—Device Type Assembly Date (YYWW) D-GM Rev. 1.3 Si5023 Temperature – ° Year WW = Work week 25 ...
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... Si5023 8. Package Outline Figure 22 illustrates the package details for the Si5023. Table 10 lists the values for the dimensions shown in the illustration. For a pad layout recommendation please contact Silicon Laboratories. Figure 22. 28-Lead Quad Flat No-Lead (QFN) Controlling Dimension: mm Symbol θ aaa bbb ...
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... Revision 1.22 to Revision 1.23 Updated Table 2 on page 7. Added “Output Common Mode Voltage (Si5023) (DOUT)” with updated values. Added “Output Common Mode Voltage (Si5023) (CLKOUT)” with updated values. Updated Table 3 on page 8. Added “Output Clock Duty Cycle OC-48/12/3” ...
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... Si5023 C I ONTACT NFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 7801 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: HighSpeed@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. ...