W134SH Cypress Semiconductor Corp, W134SH Datasheet - Page 7

• Manufacturer Part Number: W134SH
• Description: IC CLK GEN DIR RAMBUS 3.3V24QSOP
• Manufacturer: Cypress Semiconductor Corp
• Type: Direct RAMbus Clock Generatorr

Specifications of W134SH

• Output: RSL
• Frequency - Max: 400MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 24-QSOP
• Frequency-max: 400MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Input: -
• Other names: 428-1475

Document #: 38-07426 Rev. *B
Table 8. State Transition Latency Specifications (continued)
Figure 5 shows that the Clk Stop to Normal transition goes
through three phases. During t
specified and can have glitches. For t
clock output is enabled and must be glitch-free. For
t > t
50 ps of the phase before the clock output was disabled. At
this time, the clock output must also meet the voltage and
timing specifications of Table . The outputs are in a
high-impedance state during the Clk Stop mode.
Table 9. Distributed Loop Lock Time Specification
Table 10.Supply and Reference Current Specification
I
I
I
I
I
Transition
POWERDOWN
CLKSTOP
NORMAL
REF,PWDN
REF,NORM
Parameter
t
DISTLOCK
Parameter
CLKSETL
B,D
E
E
N
F
L
, the clock output phase must be settled to within
Time from when Clk/ClkB output is settled to when the phase error between SynclkN and
PclkM falls within the t
Normal or Clk Stop Power-down t
“Supply” current in Power-down state (PwrDnB 1 = 0)
“Supply” current in Clk Stop state (StopB = 0)
“Supply” current in Normal state (StopB = 1,PwrDnB = 1)
Current at VDDIR or VDDIPD reference pin in Power-down state (PwrDnB = 0)
Current at VDDIR or VDDIPD reference pin in Normal or Clk Stop state (PwrDnB = 1)
Clk Stop
Clk Stop
Normal
Normal
From
Test
CLKON
ERR,PD
CLKON
, the clock output is not
Clk Stop
Normal
Normal
Normal
Test
To
< t < t
spec in Table .
CLKSETL
Parameter
Transition Latency
t
POWERDN
Description
t
CLKSETL
t
CLKOFF
CLKON
t
t
Description
CTL
CTL
, the
20 cycles Time from StopB to Clk/ClkB output settled to within 50
10 ns
Max.
3 ms
3 ms
1 ms
5 ns
Time from StopB until Clk/ClkB provides glitch-free
clock edges.
ps of the phase before CLK/CLKB was disabled.
Time from StopB to Clk/ClkB output disabled.
Time from when S0 or S1 is changed until CLK/CLKB
output has resettled (excluding t
Time from when S0 or S1 is changed until CLK/CLKB
output has resettled (excluding t
Time from PwrDnB to the device in Power-down.
Description
W134M/W134S
Min.
Min.
DISTLOCK
DISTLOCK
–
–
–
–
–
Max.
Max.
250
100
65
50
5
Page 7 of 12
2
).
).
Unit
Unit
mA
mA
mA
ms
µA
µA