W134SH Cypress Semiconductor Corp, W134SH Datasheet - Page 2

• Manufacturer Part Number: W134SH
• Description: IC CLK GEN DIR RAMBUS 3.3V24QSOP
• Manufacturer: Cypress Semiconductor Corp
• Type: Direct RAMbus Clock Generatorr

Specifications of W134SH

• Output: RSL
• Frequency - Max: 400MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 24-QSOP
• Frequency-max: 400MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Input: -
• Other names: 428-1475

Document #: 38-07426 Rev. *B
Pin Definitions
REFCLK
PCLKM
SYNCLKN
STOPB
PWRDNB
MULT 0:1
CLK, CLKB
S0, S1
NC
VDDIR
VDDIPD
VDD
GND
Pin Name
4, 5, 8, 13, 17,
3, 9, 16, 22
15, 14
20, 18
24, 23
No.
12
19
21
11
10
2
6
7
1
RefV Reference for REFCLK. Voltage reference for input reference clock.
RefV Reference for Phase Detector. Voltage reference for phase detector inputs and StopB.
Type
O
G
P
–
W133
W158
W159
W161
W167
CY2210
I
I
I
I
I
I
I
RMC
Pclk
Reference Clock Input. Reference clock input, normally supplied by a system frequency
synthesizer (Cypress W133).
Phase Detector Input. The phase difference between this signal and SYNCLKN is used
to synchronize the Rambus Channel Clock with the system clock. Both PCLKM and
SYNCLKN are provided by the Gear Ratio Logic in the memory controller. If Gear Ratio
Logic is not used, this pin would be connected to Ground.
Phase Detector Input. The phase difference between this signal and PCLKM is used to
synchronize the Rambus Channel Clock with the system clock. Both PCLKM and
SYNCLKN are provided by the Gear Ratio Logic in the memory controller. If Gear Ratio
Logic is not used, this pin would be connected to Ground.
Clock Output Enable. When this input is driven to active LOW, it disables the differential
Rambus Channel clocks.
Active LOW Power-down. When this input is driven to active LOW, it disables the differ-
ential Rambus Channel clocks and places the W134M/W134S in power-down mode.
PLL Multiplier Select. These inputs select the PLL prescaler and feedback dividers to
determine the multiply ratio for the PLL for the input REFCLK.
Complementary Output Clock. Differential Rambus Channel clock outputs.
Mode Control Input. These inputs control the operating mode of the W134M/W134S.
No Connect
Power Connection. Power supply for core logic and output buffers. Connected to 3.3V
supply.
Ground Connection. Connect all ground pins to the common system ground plane.
Refclk
Figure 1. DDLL System Architecture
MULT0
0
0
1
1
W134M/W134S
PLL
M
Gear
Ratio
Logic
N
Phase
Align
S0
0
0
1
1
D
Synclk
MULT1
0
1
1
0
4
Description
DLL
RAC
S1
Busclk
0
1
0
1
PLL/REFCLK
W134M
5.333
4.5
6
8
Output Enable Test
Normal
Bypass
MODE
Test
W134M/W134S
PLL/REFCLK
W134S
5.333
4
6
8
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