MAX3676EHJ+T Maxim Integrated Products, MAX3676EHJ+T Datasheet - Page 8

• Manufacturer Part Number: MAX3676EHJ+T
• Description: IC CLOCK RECOVERY 32-TQFP
• Manufacturer: Maxim Integrated Products
• Type: Clock and Data Recovery (CDR)r

Specifications of MAX3676EHJ+T

• Input: PECL
• Output: PECL
• Frequency - Max: 622MHz
• Voltage - Supply: 3 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-TQFP, 32-VQFP
• Frequency-max: 622MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

622Mbps, 3.3V Clock-Recovery and
Data-Retiming IC with Limiting Amplifier
The phase detector produces a voltage proportional to
the phase difference between the incoming data and
the internal clock. Because of its feedback nature, the
PLL drives the error voltage to zero, aligning the recov-
ered clock to the incoming data. The external phase
adjustment pins (PHADJ+, PHADJ-) allow the user to
vary the internal phase alignment.
The frequency detector incorporated into the PLL uses
the input data stream edges to sample the quadrature
components of the VCO clock. This generates a differ-
ence frequency that aids acquisition during startup.
Depending on the polarity of the difference frequency,
the PFD drives the VCO so that the difference frequen-
cy is reduced to zero. Once frequency acquisition is
obtained, the frequency detector returns to a neutral
state.
The VCO is fully integrated, while the loop filter requires
an external capacitor (C
the bandwidth and peaking of the second-order PLL.
The RSSI output voltage is insensitive to temperature
and supply fluctuations. The power detector functions
as a broadband power meter that detects the total RMS
power of all signals within the detector bandwidth
(including input signal noise). The RSSI voltage varies
linearly (in decibels) for inputs of 2mV
The slope over this input range is approximately
26mV/dB.
The high-speed RSSI signal is filtered to an RMS level
with one external capacitor tied from CFILT to V
impedance looking into CFILT is about 500Ω to V
a result, the lower -3dB cutoff frequency is set by the
following simple relationship:
For 622Mbps applications, Maxim recommends a cut-
off frequency of 6.8kHz, which requires C
The RSSI output is designed to drive a minimum load
resistance of 100kΩ to ground and a maximum of
20pF. Loads greater than 20pF must be buffered by a
series resistance of 100kΩ (i.e., voltmeter).
The on-chip limiting amplifier provides more than 42dB
of gain. A low-frequency feedback loop is integrated
8
__________________Design Procedure
_______________________________________________________________________________________
Received-Signal-Strength Indicator
f
FILT
= 1/[2π(500)C
F
). This filter network determines
Input Offset Correction
Loop Filter and VCO
Frequency Detector
FILT
Phase Detector
]
P-P
FILT
to 50mV
= 47nF.
CC
CC
. The
. As
P-P
.
into the MAX3676 to remove the input offset. DC-cou-
pling to the ADI+ and ADI- inputs is not allowed, as this
would prevent the proper functioning of the DC offset-
correction circuitry.
The differential input impedance (Z
2.5kΩ. The impedance between OLC+ and OLC- (Z
is approximately 120kΩ. Take care when setting the
combined low-frequency cutoff (f
input DC-blocking capacitor (C
tion loop capacitor (C
values of C
These values ensure that the poles associated with C
and C
lower -3dB corner frequency (no gain peaking).
C
or better in order to minimize f
must be a capacitor of type Z5U or better.
An LOP monitor with a user-programmable threshold
and a hysteresis comparator is also included with the
limiting amplifier circuitry. Internally, one comparator
input is tied to the RSSI output signal, and the other is
tied to the threshold voltage (V
nally and provides a trip point for the LOP indication. A
low-voltage, low-drift op amp, referenced to an internal
bandgap voltage (1.23V), is supplied for programming
a supply independent threshold voltage. This op amp
requires two external resistors to program the LOP trip
point. V
the equation:
The op amp can source only 100μA of current.
Therefore, an R1 value of 20kΩ is recommended for
proper operation. The input bias current of the op amp
at the INV pin is less than ±100nA.
Table 1. Setting the Low-Frequency Cutoff
IN
must be a low-TC, high-quality capacitor of type X7R
0.022μF
0.010μF
6800pF
4700pF
2200pF
1000pF
OLC
470pF
330pF
220pF
C
TH
IN
work together to provide a flat response at the
IN
is programmable from 1.23V to 2.6V using
and C
V
TH
OLC
= 1.23(1 + R2/R1)
OLC
.
0.082μF
0.033μF
0.015μF
3300pF
2200pF
1500pF
0.15μF
0.01μF
). See Table 1 for selecting the
C
0.1μF
Loss-of-Power Monitor
OLC
CUTOFF
IN
TH
) and the offset correc-
), which is set exter-
CUTOFF
IN
) is approximately
COMBINED LOW
deviations. C
f
CUTOFF
), due to the
13.5
135
190
290
3.0
6.8
10
29
68
(kHz)
OLC
OLC
IN
)