SI5364-H-GL Silicon Laboratories Inc, SI5364-H-GL Datasheet - Page 29

• Manufacturer Part Number: SI5364-H-GL
• Description: IC CLOCK SONET/SDH PORT 99LFBGA
• Manufacturer: Silicon Laboratories Inc

Specifications of SI5364-H-GL

• Input: *
• Output: *
• Frequency - Max: *
• Voltage - Supply: *
• Operating Temperature: *
• Mounting Type: Surface Mount
• Package / Case: 99-LFBGA
• Frequency-max: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

*Note: The LVTTL inputs on the Si5364 device have an internal pulldown mechanism that causes the input to default to a logic
Pin #
G10
K10
H10
J10
G9
H9
K4
K3
K6
K7
K9
J3
J4
J6
J7
J9
J1
low state if the input is not driven from an external source.
FRQSEL_1[0]
FRQSEL_1[1]
FRQSEL_2[0]
FRQSEL_2[1]
FRQSEL_3[0]
FRQSEL_3[1]
FRQSEL_4[0]
FRQSEL_4[1]
CLKOUT_1+
CLKOUT_1–
CLKOUT_2+
CLKOUT_2–
CLKOUT_3+
CLKOUT_3–
CLKOUT_4+
CLKOUT_4–
Pin Name
FSYNC
Table 10. Pin Descriptions (Continued)
I/O
O
O
O
O
O
I*
I*
I*
I*
Signal Level
See Table 3
LVTTL
LVTTL
LVTTL
LVTTL
CML
CML
CML
CML
Rev. 2.5
Differential Clock Output 1.
High-frequency output clock derived from the
selected reference source (CLKIN_A, CLKIN_B, or
REF/CLKIN_F) or from Digital hold mode.
The frequencies of the Si5364 clock outputs are
each 1, 8, or 32x multiple of the frequency of the
selected clock input. The multiplication ratio is
selected using Frequency Select (FRQSEL) control
pins associated with each clock output. An additional
scaling factor of either 238/255 or 255/238 can be
selected for FEC operation using the FEC[1:0] con-
trol pins.
Differential Clock Output 2.
See CLKOUT_1.
Differential Clock Output 3.
See CLKOUT_1.
Clock Output 4.
See CLKOUT_1.
Frequency Select—Clock Out 1.
Selects the multiplication factor between the fre-
quency of the selected clock input and the frequency
of the clock output.
The FRQSEL_1[1:0] inputs are decoded as follows:
00 = Clock Driver Power Down.
01 = 1x multiplication (19.44 MHz output typical).
10 = 8x multiplication (155.52 MHz output typical).
11 = 32x multiplication (622.08 MHz output typical.
The clock output multiplication ratios can be scaled
additionally by a factor of 255/238 or 238/255 for
FEC operation. See FEC[1:0] pin description.
Frequency Select—Clock Out 2.
See FRQSEL_1[1:0].
Frequency Select—Clock Out 3.
See FRQSEL_1[1:0].
Frequency Select—Clock Out 4.
See FRQSEL_1[1:0].
Frame Sync Clock.
Nominally 8 kHz based on a 19.44 MHz reference.
The 8 kHz frame sync is disabled when 255/238 FEC
scaling of the clock output frequencies is selected.
See FEC[1:0] pin description.
Description
Si5364
29