SI5321-H-GL Silicon Laboratories Inc, SI5321-H-GL Datasheet - Page 27

• Manufacturer Part Number: SI5321-H-GL
• Description: IC CLOCK MULT SONET/SDH 63LFBGA
• Manufacturer: Silicon Laboratories Inc

Specifications of SI5321-H-GL

• Input: *
• Output: *
• Frequency - Max: *
• Voltage - Supply: *
• Operating Temperature: *
• Mounting Type: Surface Mount
• Package / Case: 63-LFBGA
• Frequency-max: *
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.465V
• Operating Temp Range: -20C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

*Note: The LVTTL inputs on the Si5321 device have an internal pulldown mechanism that causes the input to default to a
Pin #
B1
C1
D2
B4
logic low state if the input is not driven from an external source.
FXDDELAY
BWBOOST
Pin Name
BWSEL[0]
BWSEL[1]
Table 10. Si5321 Pin Descriptions (Continued)
I/O
I*
I*
I*
Signal Level
LVTTL*
LVTTL*
LVTTL*
Rev. 2.5
Bandwidth Select.
BWSEL[1:0] pins set the bandwidth of the loop filter
within the DSPLL to 6400, 3200, 1600, or 800 Hz as
indicated below.
00 = 3200 Hz
01 = 1600 Hz
10 = 800 Hz
11 = 6400 Hz
Note: The loop filter bandwidth is twice the value
Bandwidth Boost.
Active high input to boost the selected bandwidth
2x. When this pin is high the loop filter bandwidth
selected on BWSEL[1:0] is doubled. When this pin
is high, FXDDELAY must also be high and FEC[2:0]
must be 000.
Fixed Delay Mode.
Set high to disable hitless recovery from digital hold
mode. This configuration is useful in applications
that require a known or constant input-to-output
phase relationship.
When this pin is high, hitless switching from digital
hold mode back to a valid clock input is disabled.
When switching from digital hold mode to a valid
clock input with FXDDELAY high, the clock output
changes as necessary to re-establish the initial/
default input-to-output phase relationship that is
established after powerup or reset. The rate of
change is determined by the setting of BWSEL[1:0].
When this pin is low, hitless switching from Digital
Hold mode back to a valid clock input is enabled.
When switching from digital hold mode to a valid
clock input with FXDDELAY low, the device enables
“phase build out” to absorb the phase difference
between the clock output and the clock input so that
the phase change at the clock output is minimized.
In this case, the input-to-output phase relationship
following the transition out of digital hold mode is
determined by the phase relationship at the time
that switching occurs.
Note: FXDDELAY should remain at a static high or static
indicated here when BWBOOST is set high.
low level during normal operation. Transitions on
this pin are allowed only when the RSTN/CAL pin
is low. FXDDELAY must be set high when
BWBOOST is set high.
Description
Si5321
27