SI5321-H-GL Silicon Laboratories Inc, SI5321-H-GL Datasheet - Page 11

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SI5321-H-GL

Manufacturer Part Number
SI5321-H-GL
Description
IC CLOCK MULT SONET/SDH 63LFBGA
Manufacturer
Silicon Laboratories Inc
Datasheet

Specifications of SI5321-H-GL

Input
*
Output
*
Frequency - Max
*
Voltage - Supply
*
Operating Temperature
*
Mounting Type
Surface Mount
Package / Case
63-LFBGA
Frequency-max
*
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3.135V
Operating Supply Voltage (max)
3.465V
Operating Temp Range
-20C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

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Part Number
Manufacturer
Quantity
Price
Part Number:
SI5321-H-GL
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Part Number:
SI5321-H-GL
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
Company:
Part Number:
SI5321-H-GL
Quantity:
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Company:
Part Number:
SI5321-H-GL
Quantity:
10
Table 4. AC Characteristics (PLL Performance Characteristics) (Continued)
(V
Wander/Jitter at 1600 Hz Bandwidth
(BWSEL[1:0] = 01 and BWBOOST = 0; FXDDELAY = 1)
Jitter Tolerance (see Figure 9)
CLKOUT RMS Jitter Generation
FEC[2:0] = 000
CLKOUT RMS Jitter Generation
FEC[2:0] = 001, 010, 100, 101, 110, 111
CLKOUT Peak-Peak Jitter Generation
FEC[2:0] = 000
CLKOUT Peak-Peak Jitter Generation
FEC[2:0] = 001, 010, 100, 101, 110, 111
Jitter Transfer Bandwidth (see Figure 6)
Wander/Jitter Transfer Peaking
Wander/Jitter at 3200 Hz Bandwidth
(BWSEL[1:0] = 01 and BWBOOST = 1; FXDDELAY = 1)
Jitter Tolerance (see figure 7)
CLKOUT RMS Jitter Generation
FEC[2:0] = 000
CLKOUT Peak-Peak Jitter Generation
FEC[2:0] = 000
Jitter Transfer Bandwidth (see Figure 6)
Notes:
DD33
1. Higher PLL bandwidth settings provide smaller clock output wander with temperature gradient.
2. For reliable device operation, temperature gradients should be limited to 10 °C/min.
3. Telcordia GR-1244-CORE requirements specify maximum phase transient slope during clock rearrangement in terms
= 3.3 V ±5%, TA = –20 to 85 °C)
of nanoseconds per millisecond. The equivalent ps/μs unit is used here since the maximum phase transient magnitude
for the Si5321 (tPT_MTIE) never reaches one nanosecond.
Parameter
J
J
J
J
J
J
Symbol
J
GEN(RMS)
GEN(RMS)
GEN(RMS)
GEN(PP)
GEN(PP)
GEN(PP)
TOL(PP)
F
F
J
BW
BW
P
Rev. 2.5
12 kHz to 20 MHz,
50 kHz to 80 MHz,
12 kHz to 20 MHz,
50 kHz to 80 MHz,
12 kHz to 20 MHz,
50 kHz to 80 MHz,
12 kHz to 20 MHz,
50 kHz to 80 MHz,
12 kHz to 20 MHz,
50 kHz to 80 MHz,
12 kHz to 20 MHz
50 kHz to 80 MHz
Test Condition
BW = 1600 Hz
BW = 3200 Hz
f = 1600 Hz
f = 3200 Hz
f = 160 Hz
< 1600 Hz
f = 320 Hz
f = 32 Hz
f = 16 Hz
1000
Min
100
500
10
50
5
1600
3200
0.27
0.27
0.25
Typ
0.8
0.9
6.7
3.0
6.5
3.0
0.0
0.8
6.1
3.0
Si5321
Max Unit
0.35
0.35
10.0
10.0
10.0
1.2
1.2
5.0
5.0
0.1
1.0
0.3
5.0
Hz
dB
Hz
ns
ns
ns
ns
ps
ps
ps
ps
ps
ps
ps
ps
ns
ns
ps
ps
ps
ps
11

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