SI5319C-C-GM Silicon Laboratories Inc, SI5319C-C-GM Datasheet - Page 14

• Manufacturer Part Number: SI5319C-C-GM
• Description: IC CLOCK MULT/ATTENUATOR 36QFN
• Manufacturer: Silicon Laboratories Inc

Specifications of SI5319C-C-GM

• Input: *
• Output: *
• Frequency - Max: *
• Voltage - Supply: *
• Operating Temperature: *
• Mounting Type: Surface Mount
• Package / Case: 36-VFQFN Exposed Pad
• Frequency-max: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Si5319
2. Typical Phase Noise Plots
The following typical phase noise plot was taken using a Rohde and Schwarz SML03 RF Generator as the clock
input source to the Si5326. The Agilent model E5052B was used for the phase noise measurement. For this
measurement, the Si5319 operates at 3.3 V with an ac coupled differential PECL output and an ac coupled
differential sine wave input from the RF generator at 0 dBm. Note that, as with any PLL, the output jitter that is
below the loop BW is caused by the jitter at the input clock. The loop BW was 120 Hz.
2.1. Example: SONET OC-192
T
14
SONET_OC48, 12 kHz to 20 MHz
SONET_OC192_A, 20 kHz to 80 MHz
SONET_OC192_B, 4 to 80 MHz
SONET_OC192_C, 50 kHz to 80 MHz
Brick Wall, 800 Hz to 80 MHz
Figure 3. Typical Phase Noise Plot
Jitter Band
Rev. 1.0
Jitter, RMS
274 fs
274 fs
250 fs
166 fs
267 fs