SI5315A-C-GMR Silicon Laboratories Inc, SI5315A-C-GMR Datasheet - Page 34

• Manufacturer Part Number: SI5315A-C-GMR
• Description: IC CLK MULT 8KHZ-644.53MHZ 36QFN
• Manufacturer: Silicon Laboratories Inc

Specifications of SI5315A-C-GMR

• Input: *
• Output: *
• Frequency - Max: *
• Voltage - Supply: *
• Operating Temperature: *
• Mounting Type: Surface Mount
• Package / Case: 36-VQFN
• Frequency-max: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Si5315
4.4. Alarms
Summary alarms are available to indicate the overall status of the input signals. Alarm outputs stay high until all the
alarm conditions for that alarm output are cleared.
4.4.1. Loss-of-Signal
The device has loss-of-signal circuitry that continuously monitors CKINn for missing pulses. The LOS circuitry
generates an internal LOSn_INT output signal that is processed with other alarms to generate LOS1 and LOS2.
An LOS condition on CKIN1 causes the internal LOS1_INT alarm to become active. Similarly, an LOS condition on
CKINn causes the LOSn_INT alarm to become active. Once a LOSn_INT alarm is asserted on one of the input
clocks, it remains asserted until that input clock is validated over a designated time period. The time to clear
LOSn_INT after a valid input clock appears is listed in Table 3, “AC Characteristics”. If another error condition on
the same input clock is detected during the validation time then the alarm remains asserted and the validation time
starts over.
4.4.1.1. LOS Algorithm
The LOS circuitry divides down each input clock to produce an 8 kHz to 2 MHz signal. The LOS circuitry over
samples this divided down input clock using a 40 MHz clock to search for extended periods of time without input
clock transitions. If the LOS monitor detects twice the normal number of samples without a clock edge, a
LOSn_INT alarm is declared. Table 3, “AC Characteristics” gives the minimum and maximum amount of time for
the LOS monitor to trigger.
4.4.1.2. Lock Detect
The PLL lock detection algorithm indicates the lock status on the LOL output pin. The algorithm works by
continuously monitoring the phase of the input clock in relation to the phase of the feedback clock. If the time
between two consecutive phase cycle slips is greater than the retrigger time, the PLL is in lock. The LOL output
has a guaranteed minimum pulse width as shown in (Table 3, “AC Characteristics”). The LOL pin is also held in the
active state during an internal PLL calibration. The retrigger time is automatically set based on the PLL closed loop
bandwidth (See Table 13).
34
PLL Bandwidth Setting (BW)
Table 13. Lock Detect Retrigger Time
1920–3840 Hz
3840–7680 Hz
960–1920 Hz
120–240 Hz
240–480 Hz
480–960 Hz
60–120 Hz
Rev. 0.26
Retrigger Time (ms)
0.833
26.5
13.3
1.66
6.6
3.3
53