SI5315B-C-GM Silicon Laboratories Inc, SI5315B-C-GM Datasheet - Page 50

• Manufacturer Part Number: SI5315B-C-GM
• Description: IC CLOCK MULT 8KHZ-125MHZ 36QFN
• Manufacturer: Silicon Laboratories Inc

Specifications of SI5315B-C-GM

• Input: *
• Output: *
• Frequency - Max: *
• Voltage - Supply: *
• Operating Temperature: *
• Mounting Type: Surface Mount
• Package / Case: 36-VQFN
• Frequency-max: *
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: QFN EP
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Si5315
50
Pin #
GND
PAD
27
26
25
24
29
28
33
30
34
35
36
Pin Name
FRQSEL3
FRQSEL2
FRQSEL1
FRQSEL0
CKOUT1–
CKOUT1+
CKOUT2–
CKOUT2+
SFOUT0
SFOUT1
GND
NC
GND
Table 18. Si5315 Pin Descriptions (Continued)
I/O
—
O
O
I
I
Signal Level
3-Level
3-Level
Supply
Multi
Multi
—
Rev. 0.26
Frequency Select.
Three level inputs that select the input clock and clock multi-
plication ratio, depending on the FRQTBL setting.
These pins have both weak pull-ups and weak pull-downs
and default to M.
Some designs may require an external resistor voltage
divider when driven by an active device that will tri-state.
Clock Output 1.
Differential output clock with a frequency selected from a
table of values. Output signal format is selected by SFOUT
pins. Output is differential for LVPECL, LVDS, and CML com-
patible modes. For CMOS format, both output pins drive
identical single-ended clock outputs.
Signal Format Select.
Three level inputs that select the output signal format (com-
mon mode voltage and differential swing) for both CKOUT1
and CKOUT2.
These pins have both weak pull-ups and weak pull-downs
and default to M.
Some designs may require an external resistor voltage
divider when driven by an active device that will tri-state.
Clock Output 2.
Differential output clock with a frequency selected from a
table of values. Output signal format is selected by SFOUT
pins. Output is differential for LVPECL, LVDS, and CML com-
patible modes. For CMOS format, both output pins drive
identical single-ended clock outputs.
No Connect.
Leave floating. Make no external connections to this pin for
normal operation.
Ground Pad.
The ground pad must provide a low thermal and electrical
impedance to a ground plane.
SFOUT[1:0]
MM
HH
HM
MH
ML
LM
HL
LH
LL
Description
LVPECL
Reserved
LVDS
CML
Reserved
LVDS—Low Swing
CMOS
Disable
Reserved
Signal Format