TFF1003HN/N1,118 NXP Semiconductors, TFF1003HN/N1,118 Datasheet - Page 5

• Manufacturer Part Number: TFF1003HN/N1,118
• Description: IC FREQUENCY GEN TX/TXRX 24HVQFN
• Manufacturer: NXP Semiconductors
• Type: Ku Frequency Generatorr

Specifications of TFF1003HN/N1,118

• Input: Clock
• Output: Clock
• Frequency - Max: 13.05GHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-TQFN Exposed Pad
• Frequency-max: 13.05GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935286803118

NXP Semiconductors
10. Functional description
TFF1003HN_1
Product data sheet
10.1 PLL
Table 4.
The TFF1003HN consists of the following blocks:
The functionality of the blocks will be discussed below.
The PLL is formed by the VCO, DIVIDER (possible settings: 16, 32, 64, 128 and 256
(see
voltage: VREGVCO (pin 1).
The loop filter can be set to type 2 or type 3. If a type 2 filter is used, the pins
CPOUT (pin 2) and VTUNE (pin 3) must be interconnected. A 10 pF capacitor is placed
internally between pins CPOUT (pin 2) and VREGVCO (pin 1), and a 30 pF capacitor is
placed between pins VTUNE (pin 3) and VREGVCO (pin 1). See
Values for the loop filter components are given in
The VCO input voltage range is between 0.1 and 0.9 V
Symbol
V
GND2(BUF) 19
BUF1_N
BUF2_N
BUF1_P
BUF2_P
GND3(BUF) 24
•
•
•
•
•
CC(BUF)
PLL
Output buffer
Lock detector
Reference input
Divider settings
Table
Pin description
8)) and a PFD/CP. The tune voltage is referred to the band gap regulated
Pin Description
18
20
21
22
23
All information provided in this document is subject to legal disclaimers.
Supply voltage for the RF output buffer. Decouple this pin against GND2(BUF)
(pin 19).
Ground for RF output. Connect this pin to the exposed diepad landing.
RF output.
RF output.
RF output.
RF output.
Ground for RF output. Connect this pin to the exposed diepad landing.
Rev. 01 — 19 May 2010
…continued
Low phase noise LO generator for VSAT applications
Table
O(reg)VCO
5.
.
TFF1003HN
Figure 4
© NXP B.V. 2010. All rights reserved.
and
Figure
5 of 17
5.