DS26503LN+ Maxim Integrated Products, DS26503LN+ Datasheet - Page 34
DS26503LN+
Manufacturer Part Number
DS26503LN+
Description
IC T1/E1/J1 BITS ELEMENT 64-LQFP
Manufacturer
Maxim Integrated Products
Type
BITS Elementr
Datasheet
1.DS26503L.pdf
(122 pages)
Specifications of DS26503LN+
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Frequency-max
-
Output
-
Input
-
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7.3.1 Power-Up Sequence
The DS26503 contains an on-chip power-up reset function, which automatically clears the writeable
register space immediately after power is supplied to the device. The user can issue a chip reset at any
time. Issuing a reset will disrupt signals flowing through the DS26503 until the device is reprogrammed.
The reset can be issued through hardware using the TSTRST pin or through software using the SFTRST
function in the master mode register. The LIRST (LIC2.6) should be toggled from zero to one to reset the
line interface circuitry. (It will take the DS26503 about 40ms to recover from the LIRST bit being
toggled.)
7.3.2 Test Reset Register
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
HW
Mode
Bit 0: Software-Issued Reset (SFTRST). A zero-to-one transition causes the register space in the DS26503 to be cleared. A
reset clears all configuration and status registers. The bit automatically clears itself when the reset has completed.
Bits 1, 2, 3, 6, 7: Unused, must be set = 0 for proper operation.
Bits 4 and 5: Test Mode Bits (TEST0, TEST1). Test modes are used to force the output pins of the DS26503 into known
states. This can facilitate the checkout of assemblies during the manufacturing process and also be used to isolate devices from
shared buses.
TEST1
0
0
1
1
TEST0
—
X
7
0
0
1
0
1
Operate normally
Force all output pins into three-state (including all I/O pins and parallel port pins)
Force all output pins low (including all I/O pins except parallel port pins)
Force all output pins high (including all I/O pins except parallel port pins)
—
TSTRREG
Test Reset Register
00h
X
6
0
TEST1
X
5
0
TEST0
X
4
0
Effect On Output Pins
34 of 122
—
X
3
0
—
X
2
0
—
X
DS26503 T1/E1/J1 BITS Element
1
0
SFTRST
X
0
0
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