LE58QL02FJC Zarlink, LE58QL02FJC Datasheet - Page 29

• Manufacturer Part Number: LE58QL02FJC
• Description: SLIC 4-CH 3.3V 44-Pin PLCC Tube
• Manufacturer: Zarlink

Specifications of LE58QL02FJC

• Package: 44PLCC
• Number Of Channels Per Chip: 4
• Minimum Operating Supply Voltage: 3.135 V
• Typical Operating Supply Voltage: 3.3 V

be routed through the CD1B latch. The LD Enable pulse allows CD1 pin data to be routed through the CD1 latch. The uncertain
states of the SLIC device’s DET output, and the masked times where that DET data is ignored are shown in this timing diagram.
Using this isolation of masked times, the CD1 and CD1B registers are guaranteed to contain accurate representations of the
SLIC device detector output.
Note:
* Transparent latches: When enable input is high, Q output follows D input. When enable input goes low, Q output is latched at last state.
MCLK/E1
MPI Command
54/55h
I/O Direction
Register
CD1
CD2
C3
C4
C5
INT
Figure 21. SLIC Device I/O E1 Multiplex and Real-Time Data Register Operation
SLIC Output
Register
MPI Command 52h
E1 Source
(Internal)
Output Latch
E1P
EE1 Bit
See Figure 22
Delay
for details
ATI
GK Enable
(Channel 1
Zarlink Semiconductor Inc.
LD Enable
Shown)
EN/HOLD
D
*
(Command 70/71h)
29
Q
{
MCDB
EN/HOLD
D
Channels
Same for
2, 3, 4
—
4
*
MCDA
Q
SLIC Input Register
MPI Command 53h
— CD1B C5
CDB
4
(time set via Command
MCDB
Ground Key Filter
1
4
CDA
3
E8/E9h)
MCDA
0
4
(Command 6C/6Dh)
(Command 4D/4Fh)
MUX
CDB
Interrupt Mask
Data Register
3
C4
Register
Real Time
MCDB
3
CDA
C3 CD2 CD1
3
2
(time set via Command
MCDA
CDB
2
Debounce
2
CDA
C8/C9h)
MCDB
2
CDB
1
MCDA
1
CDA
1
1