DS92LV090ATVEH/HAPB National Semiconductor, DS92LV090ATVEH/HAPB Datasheet - Page 6

• Manufacturer Part Number: DS92LV090ATVEH/HAPB
• Manufacturer: National Semiconductor

Specifications of DS92LV090ATVEH/HAPB

• Number Of Elements: 1
• Operating Supply Voltage (typ): 3.3V
• Differential Output Voltage: 460mV
• Propagation Delay Time: 3.2ns
• Power Dissipation: 1.74W
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: LQFP
• Number Of Receivers: 1
• Number Of Drivers: 1
• Lead Free Status / RoHS Status: Not Compliant

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Applications Information
General application guidelines and hints may be found in the
following application notes: AN-808, AN-903, AN-971,
AN-977, and AN-1108.
There are a few common practices which should be implied
when designing PCB for Bus LVDS signaling. Recommended
practices are:
•
•
•
•
•
•
MEDIA (CONNECTOR or BACKPLANE) SELECTION:
•
Test Circuits and Timing Waveforms
Use at least 4 PCB board layer (Bus LVDS signals,
ground, power and TTL signals).
Keep drivers and receivers as close to the (Bus LVDS port
side) connector as possible.
Bypass each Bus LVDS device and also use distributed
bulk capacitance between power planes. Surface mount
capacitors placed close to power and ground pins work
best. Two or three high frequency, multi-layer ceramic
(MLC) surface mount (0.1 µF, 0.01 µF, 0.001 µF) in parallel
should be used between each V
capacitors should be as close as possible to the V
Multiple vias should be used to connect V
planes to the pads of the by-pass capacitors.
In addition, randomly distributed by-pass capacitors
should be used.
Use the termination resistor which best matches the
differential impedance of your transmission line.
Leave unused Bus LVDS receiver inputs open (floating).
Limit traces on unused inputs to <0.5 inches.
Isolate TTL signals from Bus LVDS signals
Use controlled impedance media. The backplane and
connectors should have a matched differential
impedance.
FIGURE 2. Differential Driver Propagation Delay and Transition Time Test Circuit
CC
and ground. The
FIGURE 1. Differential Driver DC Test Circuit
CC
and Ground
CC
pin.
6
X = High or Low logic state
L = Low state
Z = High impedance state
H = High state
RE
DE
H
L
L
L
H
H
H
L
LOOP BACK MODE
MODE SELECTED
TRI-STATE MODE
RECEIVER MODE
DRIVER MODE
−100 mV < V
TABLE 2. Transmitter Mode
TABLE 1. Functional Table
INPUTS
0.8V< D
TABLE 3. Receiver Mode
INPUTS
H (> +100 mV)
L (< −100 mV)
(RI+) – (RI−)
D
10011104
H
X
L
IN
IN
<2.0V
X
ID
10011103
< +100 mV
DE
H
H
L
L
DO+
H
X
Z
L
OUTPUTS
OUTPUT
DO−
RE
H
X
L
Z
H
H
H
L
X
Z
L
L