DS92LV090ATVEH/HAPB National Semiconductor, DS92LV090ATVEH/HAPB Datasheet

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DS92LV090ATVEH/HAPB

Manufacturer Part Number
DS92LV090ATVEH/HAPB
Description
Manufacturer
National Semiconductor
Datasheet

Specifications of DS92LV090ATVEH/HAPB

Number Of Elements
1
Operating Supply Voltage (typ)
3.3V
Differential Output Voltage
460mV
Propagation Delay Time
3.2ns
Power Dissipation
1.74W
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
64
Package Type
LQFP
Number Of Receivers
1
Number Of Drivers
1
Lead Free Status / RoHS Status
Not Compliant
© 2007 National Semiconductor Corporation
DS92LV090A
9 Channel Bus LVDS Transceiver
General Description
The DS92LV090A is one in a series of Bus LVDS transceivers
designed specifically for the high speed, low power propri-
etary backplane or cable interfaces. The device operates from
a single 3.3V power supply and includes nine differential line
drivers and nine receivers. To minimize bus loading, the driver
outputs and receiver inputs are internally connected. The
separate I/O of the logic side allows for loop back support.
The device also features a flow through pin out which allows
easy PCB routing for short stubs between its pins and the
connector.
The driver translates 3V TTL levels (single-ended) to differ-
ential Bus LVDS (BLVDS) output levels. This allows for high
speed operation, while consuming minimal power with re-
duced EMI. In addition, the differential signaling provides
common mode noise rejection of ±1V.
The receiver threshold is less than ±100 mV over a ±1V com-
mon mode range and translates the differential Bus LVDS to
standard (TTL/CMOS) levels. (See Applications Information
Section for more details.)
Simplified Functional Diagram
TRI-STATE
®
is a registered trademark of National Semiconductor Corporation.
100111
Features
Bus LVDS Signaling
3.2 nanosecond propagation delay max
Chip to Chip skew ±800ps
Low power CMOS design
High Signaling Rate Capability (above 100 Mbps)
0.1V to 2.3V Common Mode Range for V
±100 mV Receiver Sensitivity
Supports open and terminated failsafe on port pins
3.3V operation
Glitch free power up/down (Driver & Receiver disabled)
Light Bus Loading (5 pF typical) per Bus LVDS load
Designed for Double Termination Applications
Balanced Output Impedance
Product offered in 64 pin TQFP package
High impedance Bus pins on power off (V
Driver Channel to Channel skew (same device) 230ps
typical
Receiver Channel to Channel skew (same device) 370ps
typical
10011101
December 14, 2007
ID
CC
www.national.com
= 200mV
= 0V)

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DS92LV090ATVEH/HAPB Summary of contents

Page 1

... Bus LVDS to standard (TTL/CMOS) levels. (See Applications Information Section for more details.) Simplified Functional Diagram TRI-STATE ® registered trademark of National Semiconductor Corporation. © 2007 National Semiconductor Corporation Features ■ Bus LVDS Signaling ■ 3.2 nanosecond propagation delay max ■ ...

Page 2

Connection Diagram Pin Descriptions Pin Name Pin # DO+/RI+ 27, 31, 35, 37, 41, 45, 47, 51, 55 DO−/RI− 26, 30, 34, 36, 40, 44, 46, 50 12, 18, 20, 22, 58 ...

Page 3

... Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage ( Enable Input Voltage (DE, RE) Driver Input Voltage ( Receiver Output Voltage (R ) OUT Bus Pin Voltage (DO/RI±) ESD (HBM 1.5 kΩ, 100 pF) ...

Page 4

Symbol Parameter I Power Supply Current CCD Drivers Enabled, Receivers Disabled I Power Supply Current CCR Drivers Disabled, Receivers Enabled I Power Supply Current, CCZ Drivers and Receivers TRI- STATE ® I Power Supply Current, CC Drivers and Receivers Enabled ...

Page 5

AC Electrical Characteristics Over recommended operating supply voltage and temperature ranges unless otherwise specified (Note 6) Symbol Parameter DIFFERENTIAL DRIVER TIMING REQUIREMENTS t Differential Prop. Delay High to Low (Note 8) PHLD t Differential Prop. Delay Low to High (Note ...

Page 6

Applications Information General application guidelines and hints may be found in the following application notes: AN-808, AN-903, AN-971, AN-977, and AN-1108. There are a few common practices which should be implied when designing PCB for Bus LVDS signaling. Recommended practices ...

Page 7

FIGURE 3. Differential Driver Propagation Delay and Transition Time Waveforms FIGURE 4. Driver TRI-STATE Delay Test Circuit FIGURE 5. Driver TRI-STATE Delay Waveforms 10011105 10011106 10011107 7 www.national.com ...

Page 8

FIGURE 6. Receiver Propagation Delay and Transition Time Test Circuit FIGURE 7. Receiver Propagation Delay and Transition Time Waveforms www.national.com FIGURE 8. Receiver TRI-STATE Delay Test Circuit FIGURE 9. Receiver TRI-STATE Delay Waveforms 8 10011108 10011109 10011110 10011111 ...

Page 9

Typical Bus Application Configurations Bi-Directional Half-Duplex Point-to-Point Applications Multi-Point Bus Applications 9 10011112 10011113 www.national.com ...

Page 10

Physical Dimensions www.national.com inches (millimeters) unless otherwise noted 64-Lead Molded TQFP Package Order Number DS92LV090ATVEH NS Package Number VEH064DB 10 ...

Page 11

Notes 11 www.national.com ...

Page 12

... For more National Semiconductor product information and proven design tools, visit the following Web sites at: Products Amplifiers www.national.com/amplifiers Audio www.national.com/audio Clock Conditioners www.national.com/timing Data Converters www.national.com/adc Displays www.national.com/displays Ethernet www.national.com/ethernet Interface www.national.com/interface LVDS www.national.com/lvds Power Management www.national.com/power Switching Regulators www.national.com/switchers LDOs www ...

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