SCC68692E1N40,129 NXP Semiconductors, SCC68692E1N40,129 Datasheet - Page 17

• Manufacturer Part Number: SCC68692E1N40,129
• Manufacturer: NXP Semiconductors

Specifications of SCC68692E1N40,129

• Transmitter And Receiver Fifo Counter: No
• Operating Supply Voltage (typ): 5V
• Package Type: PDIP
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Mounting: Through Hole
• Pin Count: 40
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Supply Current: 10mA
• Number Of Channels: 2
• Lead Free Status / RoHS Status: Compliant

Philips Semiconductors
OPCR[1:0] – OP2 Output Select
This field programs the OP2 output to provide one of the following:
00 The complement of OPR[2].
01 The 16X clock for the Channel A transmitter. This is the clock
10 The 1X clock for the Channel A transmitter, which is the clock
11 The 1X clock for the Channel A receiver, which is the clock that
ACR – Auxiliary Control Register
ACR[7] – Baud Rate Generator Set Select
This bit selects one of two sets of baud rates to be generated by the
BRG.
Set 1:
Set 2:
Table 4. Bit Rate Generator Characteristics
Crystal or Clock = 3.6864MHz
Asynchronous UART communications can tolerate frequency error
of 4.1% to 6.7% in a “clean” communications channel. The percent
of error changes as the character length changes. The above
percentages range from 5 bits not parity to 8 bits with parity and one
stop bit. The error with 8 bits no parity and one stop bit is 4.6%. If a
stop bit length of 9/16 is used, the error tolerance will approach 0
due to a variable error of up to 1/16 bit time in receiver clock phase
alignment to the start bit.
The selected set of rates is available for use by the Channel A and
B receivers and transmitters as described in CSRA and CSRB.
Baud rate generator characteristics are given in Table 4.
2004 Mar 03
NOTE: Duty cycle of 16X clock is 50% 1%.
Dual asynchronous receiver/transmitter (DUART)
BAUD RATE
selected by CSRA[3:0], and will be a 1X clock if CSRA[3:0] =
1111.
that shifts the transmitted data. If data is not being transmitted, a
free running 1X clock is output.
samples the received data. If data is not being received, a free
running 1X clock is output.
115.2K
14.4K
19.2K
28.8K
38.4K
57.6K
134.5
1050
1200
1800
2000
2400
4800
7200
9600
150
200
300
600
110
50
75
50, 110, 134.5, 200, 300, 600, 1.05k, 1.2k, 2.4k, 4.8k, 7.2k, 9.6k, and 38.4k baud.
75, 110, 134.5, 150, 300, 600, 1.2k, 1.8k, 2.0k, 2.4k, 4.8k, 9.6k, and 19.2k baud.
ACTUAL 16X CLOCK (kHz)
1,843.2
16.756
32.056
1.759
2.153
153.6
230.4
307.2
460.8
614.4
921.2
115.2
19.2
28.8
38.4
76.8
0.8
1.2
2.4
3.2
4.8
9.6
ERROR (%)
–0.069
–0.260
0.059
0.175
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
17
has no effect on the INTRN output. Note that the IMR does not mask
information is unlatched and reflects the state of the input pins at the
Register (IMR). If a bit in the ISR is a ‘1’ and the corresponding bit in
the IMR is also a ‘1’, the INTRN output will be asserted (LOW). If the
ACR[6:4] – Counter/Timer Mode And Clock Source Select
This field selects the operating mode of the counter/timer and its
clock source as shown in Table 5.
Table 5. ACR [6:4] Field Definition
ACR[3:0] – IP3, IP2, IP1, IP0 Change-of-State Interrupt Enable
This field selects which bits of the input port change register (IPCR)
cause the input change bit in the interrupt status register (ISR[7]) to
be set. If a bit is in the ‘on’ state the setting of the corresponding bit
in the IPCR will also result in the setting of ISR[7], which results in
the generation of an interrupt output if IMR[7] = 1. If a bit is in the
‘off’ state, the setting of that bit in the IPCR has no effect on ISR[7].
IPCR – Input Port Change Register
IPCR[7:4] – IP3, IP2, IP1, IP0 Change-of-State
These bits are set when a change-of-state, as defined in the input
port section of this data sheet, occurs at the respective input pins.
They are cleared when the IPCR is read by the CPU. A read of the
IPCR also clears ISR[7], the input change bit in the interrupt status
register. The setting of these bits can be programmed to generate
an interrupt to the CPU.
IPCR[3:0] – IP3, IP2, IP1, IP0 Change-of-State
These bits provide the current state of the respective inputs. The
time the IPCR is read.
ISR – Interrupt Status Register
This register provides the status of all potential interrupt sources.
The contents of this register are masked by the Interrupt Mask
corresponding bit in the IMR is a zero, the state of the bit in the ISR
the reading of the ISR – the true status will be provided regardless
of the contents of the IMR. The contents of this register are
initialized to H‘00’ when the DUART is reset.
ISR[7] – Input Port Change Status
This bit is a ‘1’ when a change-of-state has occurred at the IP0, IP1,
IP2, or IP3 inputs and that event has been selected to cause an
interrupt by the programming of ACR[3:0]. The bit is cleared when
the CPU reads the IPCR.
000
001
010
011
100
101
110
111
NOTE: Timer mode generates a squarewave.
[6:4]
Counter
Counter
Counter
Counter
Timer (square wave)
Timer (square wave)
Timer (square wave)
Timer (square wave)
MODE
External (IP2)
TxCA – 1x clock of Channel A
transmitter
TxCB – 1x clock of Channel B
transmitter
Crystal or external (x1/CLK)
divided by 16
External (IP2)
External (IP2) divided by 16
Crystal or external clock
(X1/CLK)
Crystal or IP2 clock (X1/CLK)
divided by 16
CLOCK SOURCE
SCC68692
Product data