COM20020ILJP Standard Microsystems (SMSC), COM20020ILJP Datasheet - Page 26

• Manufacturer Part Number: COM20020ILJP
• Manufacturer: Standard Microsystems (SMSC)

Specifications of COM20020ILJP

• Number Of Transceivers: 1
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 28
• Lead Free Status / RoHS Status: Not Compliant

Chapter 6
6.1
Revision 12-05-06
REGISTER
ADDRESS
ADDRESS
PTR HIGH
PTR LOW
SUB ADR
URATION
CONFIG-
NODE ID
STATUS
STATUS
NEXT ID
SETUP1
SETUP2
TENTID
DIAG.
DATA
Microsequencer
The COM20020ID contains an internal microsequencer which performs all of the control operations
necessary to carry out the ARCNET protocol. It consists of a clock generator, a 544 x 8 ROM, a program
counter, two instruction registers, an instruction decoder, a no-op generator, jump logic, and
reconfiguration logic.
The COM20020ID derives a 10 MHz and a 5 MHz clock from the output clock of the Clock Multiplier.
These clocks provide the rate at which the instructions are executed within the COM20020ID. The 10
MHz clock is the rate at which the program counter operates, while the 5 MHz clock is the rate at which the
instructions are executed. The microprogram is stored in the ROM and the instructions are fetched and
then placed into the instruction registers. One register holds the opcode, while the other holds the
immediate data. Once the instruction is fetched, it is decoded by the internal instruction decoder, at which
point the COM20020ID proceeds to execute the instruction. When a no-op instruction is encountered, the
microsequencer enters a timed loop and the program counter is temporarily stopped until the loop is
complete. When a jump instruction is encountered, the program counter is loaded with the jump address
from the ROM.
microsequencer if it has timed out. At this point the program counter is cleared and the MYRECON bit of
the Diagnostic Status Register is set.
Note 6.1
RECON
RESET
RBUS-
MODE
RI/TRI
DATA
(R/W)
MSB
TID7
NID7
TMG
NXT
MY-
RD-
ID7
D7
A7
P1
Functional Description
CCHEN
DUPID
AUTO-
FOUR
NAKS
The COM20020ID contains an internal reconfiguration timer which interrupts the
TID6
NID6
X/RI
NXT
INC
ID6
D6
A6
X
0
Table 6.1 - Read Register Summary
CKUP1
TXEN
RCV-
X/TA
NID5
TID5
ACT
NXT
ID5
A5
D5
X
X
0
DATASHEET
TOKEN
CKUP0
RCV-
NID4
POR
TID4
NXT
ET1
ALL
ID4
A4
D4
X
0
Page 26
READ
Note 6.1
(R/W)
CKP3
TEST
EXC-
NID3
TID3
NAK
NXT
ET2
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
ID3
A3
D3
EF
X
RECON
TENTID
PLANE
BACK-
SYNC
CKP2
SUB-
TID2
NID2
AD2
NXT
NO-
A10
ID2
D2
A2
NEXTID
CKP1
SUB-
SUB-
RCN-
NID1
TID1
TMA
NEW
NXT
TM1
AD1
AD1
ID1
A9
A1
D1
SMSC COM20020I Rev D
SLOW-
RCM-
SUB-
SUB-
TID0
NID0
ARB
LSB
AD0
AD0
NXT
TM2
TTA
TA/
ID0
D0
A8
A0
X
ADDR
Datasheet
07-0
07-1
07-2
07-3
07-4
00
01
02
03
04
05
06