LFX125EB-04F256I LATTICE SEMICONDUCTOR, LFX125EB-04F256I Datasheet - Page 32

• Manufacturer Part Number: LFX125EB-04F256I
• Description: FPGA ispXPGA® Family 139K Gates 1936 Cells EECMOS Technology 2.5V/3.3V 256-Pin FBGA
• Manufacturer: LATTICE SEMICONDUCTOR

Specifications of LFX125EB-04F256I

• Package: 256FBGA
• Family Name: ispXPGA®
• Device Logic Units: 1936
• Device System Gates: 139000
• Number Of Registers: 3800
• Typical Operating Supply Voltage: 2.5|3.3 V
• Maximum Number Of User I/os: 160
• Ram Bits: 94208
• Re-programmability Support: Yes

Lattice Semiconductor
ispXPGA 125B/C & ispXPGA 125EB/EC PFU Timing Parameters
Functional Delays
LUTs
t
t
t
Shift Register (LUT)
t
t
t
Arithmetic Functions
t
t
t
t
t
t
Feed-thru
t
Distributed RAM
t
t
t
t
t
t
t
t
t
Register/Latch Delays
Registers
t
t
t
t
t
Latches
t
t
t
t
LUT4
LUT5
LUT6
LSR_S
LSR_H
LSR_CO
LCTHRUR
LCTHRUL
LSTHRU
LSINCOUT
LCINSOUTR
LCINSOUTL
LFT
LRAM_CO
LRAMAD_S
LRAMD_S
LRAMWE_S
LRAMAD_H
LRAMD_H
LRAMWE_H
LRAMCPW
LRAMADO
L_CO
L_S
L_H
LCE_S
LCE_H
L_GO
LL_S
LL_H
LLPD
Parameter
2
4-Input LUT Delay
5-Input LUT Delay
6-Input LUT Delay
Shift Register Setup Time
Shift Register Hold Time
Shift Register Clock to Output Delay
MC (Macro Cell) Carry In to MC Carry Out Delay (Ripple)
MC Carry In to MC Carry Out Delay (Look Ahead)
MC Sum In to MC Sum Out Delay
MC Sum In to MC Carry Out Delay
MC Carry In to MC Sum Out Delay (Ripple)
MC Carry In to MC Sum Out Delay (Look Ahead)
PFU Feed-Thru Delay
Clock to RAM Output
Address Setup Time
Data Setup Time
Write Enable Setup Time
Address Hold Time
Data Hold Time
Write Enable Hold Time
Clock Pulse Width (High or Low)
Address to Output Delay
Register Clock to Output Delay
Register Setup Time (Data before Clock)
Register Hold Time (Data after Clock)
Register Clock Enable Setup Time
Register Clock Enable Hold Time
Latch Gate to Output Delay
Latch Setup Time
Latch Hold Time
Latch Propagation Delay (Transparent Mode)
Description
Over Recommended Operating Conditions
28
-0.41
-0.64
-0.12
-0.11
-0.12
Min.
0.61
0.21
0.45
0.58
0.11
0.12
2.91
0.14
0.11
0.14
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
-5
1
Max.
0.08
0.15
0.58
0.41
0.73
0.86
0.70
0.05
0.42
0.29
0.36
0.26
1.24
0.86
0.09
0.09
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ispXPGA Family Data Sheet
-0.62
-0.40
-0.12
-0.11
-0.12
Min.
0.63
0.22
0.46
0.60
0.11
0.12
3.00
0.14
0.11
0.14
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
-4
Max.
0.44
0.79
0.93
0.75
0.09
0.05
0.16
1.33
0.93
0.62
0.10
0.45
0.31
0.39
0.28
0.10
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
-0.53
-0.34
-0.10
-0.09
-0.10
Min.
0.72
0.25
0.53
0.69
0.13
0.14
3.45
0.16
0.13
0.16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
-3
Max.
0.51
0.91
1.07
0.86
0.10
0.06
0.52
0.36
0.45
0.32
0.18
1.53
1.07
0.71
0.12
0.12
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns