ZT5524A1B Intel (CPU), ZT5524A1B Datasheet
ZT5524A1B
Specifications of ZT5524A1B
ZT5524A1B Summary of contents
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Intel NetStructure MPCBL5524 High-Performance System Master Processor Board Technical Product Specification February 2006 ® ZT 5524 / Order Number: 273788-009 ...
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INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY ...
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Contents 1 Glossary ......................................................................................................................................... 9 2 Introduction.................................................................................................................................. 10 2.1 Product Definition ............................................................................................................... 10 2.2 ZT 5524 / MPCBL5524 Features........................................................................................ 11 2.3 ZT 5524 / MPCBL5524 Functional Blocks .......................................................................... 14 ® 2.3.1 Intel Pentium 2.3.2 Chipset...................................................................................................................15 2.3.2.1 ServerWorks* Champion North Bridge ...
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Contents 3.4 I/O Configuration................................................................................................................. 29 3.4.1 Analog Video Interface .......................................................................................... 32 3.5 Video BIOS ......................................................................................................................... 32 3.6 Connectivity ........................................................................................................................ 33 3.7 Switches and Build Options ................................................................................................ 33 3.8 BIOS Configuration Overview............................................................................................. 33 3.8.1 Console Redirection .............................................................................................. 34 3.9 Installing the ...
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BIOS Recovery............................................................................................................................. 52 7.1 BIOS Recovery Module ...................................................................................................... 52 7.1.1 Forcing a Boot from the BIOS Recovery Module................................................... 53 7.1.2 Flash Utility Program ............................................................................................. 53 8 System Monitoring and Alarms.................................................................................................. 54 8.1 SMBus Address Map .......................................................................................................... 54 A Specifications ...
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Contents B.2.4 CICBC- CompactPCI Interface Controller B Command Register .......................... 82 C Reset............................................................................................................................................. 84 C.1 Reset Types and Sources .................................................................................................. 84 C.1.1 Backend Power Down Sources ............................................................................. 84 C.1.2 General Reset Sources ......................................................................................... 84 C.1.3 NMI Sources .......................................................................................................... 85 D ...
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Setup Screen .............................................................................................................................. 34 5 Factory Default Switch Configuration ......................................................................................... 39 6 Customer Switch Configuration .................................................................................................. 39 7 Watchdog Timer Architecture ..................................................................................................... 5524 / MPCBL5524 Board Dimensions................................................................................. 58 9 Connector Locations................................................................................................................... 60 10 Backplane Connectors Pin ...
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Contents 42 HCINDEX Bit Descriptions ......................................................................................................... 78 43 HCDATA Bit Description............................................................................................................. 79 44 INT Bit Descriptions .................................................................................................................... 79 45 Host Control Function Registers................................................................................................. 80 46 CICAS Bit Descriptions............................................................................................................... 80 47 CICAC Bit Descriptions .............................................................................................................. 81 48 CICBS Bit Descriptions............................................................................................................... 82 ...
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Glossary BMC CIC CICBC CICBS HARST HCF HSPOR IPMI ISAWD1 ISAWD2 MRST NMI P2P PCI PBRST PCIRST PROM PWROK RST RPIO S1PBRST SEL SMM ® Intel NetStructure ZT 5524 / MPCBL5524 High-Performance System Master Processor Board TPS Baseboard Management Controller ...
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Introduction Introduction This chapter provides a brief introduction to the Intel® NetStructure System Master Processor Board. Included in this chapter: • Product definition • List of product features • ZT 5524 / MPCBL5524 Faceplate figure • ZT 5524 / MPCBL5524 ...
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Optional ZT 4901 Bridge Mezzanine boards on both processor boards provide Redundant Host (RH) functionality, dual 2Gbit Fibre Channels, dual 64/66 PMCs, and access to a second CompactPCI bus segment. 2.2 ZT 5524 / MPCBL5524 Features • CompactPCI System Master ...
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Introduction • Dual-stage watchdog timer • Push-button Reset/Abort switches • LEDs: — Status (Green/Amber) — Two User (Green/Amber/Off) — Local IDE Disk Activity (Green/Off) — Hot Swap (Blue/Off) — Power/Reset (Green/Amber/Off) — Ethernet C: •10/100 (Off/Green) •Link (Green) •Activity (Flashing ...
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Figure 1. ZT 5524 / MPCBL5524 Faceplate Ethernet C Video COM1 RS-232 Serial Port Keyboard/Mouse Power/Reset LED User LED 1 1 Ethernet A Ethernet B USB Abort Request/Alarm Cutoff Switch CPU Reset Switch Hotswap LED ® Intel NetStructure ZT 5524 ...
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Introduction 2.3 ZT 5524 / MPCBL5524 Functional Blocks Below is a functional block diagram of the ZT 5524 / MPCBL5524. The following topics provide overviews of the functional blocks. Figure 2. ZT 5524 / MPCBL5524 Functional Block Diagram Front Panel ...
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Intel Pentium The ZT 5524 / MPCBL5524 features either one or two Low Voltage (LV) Intel Pentium III 512 KByte processor(s). The Pentium III processor is a small, highly integrated assembly containing an Intel Pentium processor and its ...
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Introduction • Power management logic • Internal APIC Controller • USB Interface • SMB bus interface • Glueless Serial interface with the CNB30LE-T • 16-bit counters/timers based on 82C54 Appendix E, “Chipset,” 2.3.3 CompactPCI Bus Interface The ZT 5524 / ...
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Special features of the 21154-BE include: • Support for independent primary and secondary PCI clocks • 64-bit PCI operation • 33 MHz or 66 MHz PCI bus operation A link to the datasheet for this device is listed in Appendix ...
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Introduction • Power-On Reset (HSPOR) from the Hot Swap Controller • Power OK (PWROK) from the last stage power monitor • PCI Reset (PCIRST) from PCI Bus 0 • HA Reset (HARST) from the redundant Host • Push-button Reset (S1PBRST) ...
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All memory components and DIMMs used with the ZT 5524 / MPCBL5524 must comply with the following PC SDRAM specifications: • PC SDRAM Specification (memory component specific) • PC SDRAM Registered DIMM Specification Note: Double-stacked DIMMs may be used only ...
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Introduction The ZT 5524 / MPCBL5524’s hot swap controller unconditionally resets the board when it detects that the 3 and 12 V supplies are below an acceptable operating limit. These limits are defined as 4. ...
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Counter/timers • Serial I/O • Real-time clock • Keyboard • IDE interface • Digital I/O • CompactPCI backplane (21154) • On-board PCI devices • Floppy disk Enhanced capabilities include the ability to configure each interrupt level for active high-going ...
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Introduction Connector locations and pinouts are documented in Connectors.” 2.3.17 Counter/Timers Three counter/timers as defined for the PC/AT* are included on the ZT 5524 / MPCBL5524. Operating modes supported by the counter/timers include: • Interrupt on count • Frequency divider ...
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PC), updates the century byte to 20. This feature enables operating systems and applications using the BIOS date/time services to reliably manipulate the year as a four-digit value. A coin-cell battery ...
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Introduction The 69000 incorporates integrated SDRAM for the graphics/video frame buffer. The integrated SDRAM memory can support MHz operation, thus increasing the available memory bandwidth for the graphics subsystem. VGA-compatible video signals are available ...
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IDE disk activity (primary or secondary) • Green = active • Off = inactive User-defined LEDs—one may be defined as clock throttle • Green = user defined • Amber = user defined • Off = user defined Ethernet A, Ethernet ...
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Introduction In addition, the ZT 5524 / MPCBL5524 transitions Ethernet A and B through CompactPCI connector J3 and Ethernet C through J5. Connector locations and pinouts are documented in Connectors.” 2.4 Software This section explains key software components. 2.4.1 BIOS ...
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Redundant Host The ZT 5524 / MPCBL5524 is designed to operate as a Host in a PICMG 2.13 compliant RSS backplane. Intel’s Redundant Host Software Development Kit is fully integrated with software features, including development utilities to simulate fault ...
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Getting Started Getting Started This chapter summarizes the information you need to make the ZT 5524 / MPCBL5524 operational. Please read it before attempting to use the board. 3.1 Unpacking Check the shipping carton for damage. If the shipping carton ...
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Electrical and Environmental Requirements The ZT 5524 / MPCBL5524 requires a maximum of +5 VDC +5%, -3% @ 4.5 A with dual 933 MHz processors loaded, +5 VDC +5%, -3% @ 2.7 A with a single 933 MHz processor ...
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Getting Started Memory Address Map Example Figure 3. FFF80000 - FFFFFFFFh FEE00400 - FFF7FFFFh FEE00000 - FEE003FFh FEC02000 - FEDFFFFFh FEC01000 - FEC01FFFh FEC00000 - FEC00FFFh Top of Memory - FEBFFFFFh 00100000h -Top of Memory E0000h - FFFFFh C8000h - ...
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Table 1. I/O Address Map (Sheet ® Intel NetStructure ZT 5524 / MPCBL5524 High-Performance System Master Processor Board TPS General Purpose Chipset F50-F58h Power Management Data Register CD7h Power Management Index Register CD6h Miscellaneous Control Registers C6Fh ...
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Getting Started Table 1. I/O Address Map (Sheet 3.4.1 Analog Video Interface The ZT 5524 / MPCBL5524 provides access to video at the faceplate through J10, using the Chips and Technologies 69000 HiQVideo Accelerator with Integrated Memory, ...
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Connectivity The ZT 5524 / MPCBL5524 provides several connectors for interfacing to application-specific devices. Connector locations and pinouts are documented in Connectors.” 3.7 Switches and Build Options The ZT 5524 / MPCBL5524 provides switch configuration options for features that ...
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Getting Started Figure 4. Setup Screen 3.8.1 Console Redirection Console redirection allows users to monitor the ZT 5524 / MPCBL5524’s boot process and to run the ZT 5524 / MPCBL5524’s Setup utility from a remote serial terminal. Connection is made ...
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Installing the Operating System For more detailed information about your operating system, refer to the documentation provided by the operating system vendor and to the ZT 5524 / MPCBL5524 Product Page on the Intel website (URL listed in Appendix ...
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Getting Started 3.10 Programming the LEDS The ZT 5524 / MPCBL5524 includes two user-controlled, bi-color (amber/green), LEDs located on the connector plate (see through bits 0-3 of the Power/LED Control Register (Port E5h) (see Control (E5h)”). The LEDs are turned ...
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Table 3. Code for Modifying Bits of User LED 1 (Sheet Code in al, E5h and al, F3h out E5h, al sti ® Intel NetStructure ZT 5524 / MPCBL5524 High-Performance System Master Processor Board TPS Description ; ...
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Configuration Configuration The ZT 5524 / MPCBL5524 includes several options that tailor the operation of the board to requirements of specific applications. Most of the options are selected through the BIOS Setup mechanism (discussed in Some options cannot be software ...
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Figure 5. Factory Default Switch Configuration SW3 SW5 SW6 Figure 6. Customer Switch Configuration SW3 SW5 ...
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Configuration 4.2 Switch Descriptions The following topics present the switches in numerical order and provide a detailed description of each switch. Multiple-position switches are identified in the form SWx-N, where x is the switch number and -N is the switch ...
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Table 6. SW3-4 Settings SW3-4 Function Open Onboard IDE Master Closed (Default) Onboard IDE Slave 4.2.6 SW4-1 (Flash Write Protect/Write Enable) Closing this switch write-protects the BIOS portion of the flash memory. Open SW4-1 when installing an operating system image ...
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Configuration 4.2.9 SW4-4 (BMC Flash Write Protect) This switch allows write protection of the BMC flash. Factory default is open. Table 9. SW4-4 Settings SW4-4 Function Open (Default) Normal Operation Closed BMC Flash Write Protected 4.2.10 SW5-1, SW5-2, SW6-2 (Battery ...
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SW6-3 (Drone Reset Control) Closing SW6-3 allows the PCI Reset signal to be ignored when the ZT 5524 / MPCBL5524 is used in Drone Mode. Factory default is open. Table 12. SW6-3 Settings SW6-3 Function Open (Default) Drone PCI ...
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IDE Interface IDE Interface This chapter provides an introduction to the ZT 5524 / MPCBL5524’s IDE interface controller. It documents the ZT 5524 / MPCBL5524’s support for local and remote IDE disk drives. The ZT 5524 / MPCBL5524 supports ATA-66 ...
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Secondary IDE Channel The ZT 5524 / MPCBL5524 secondary IDE channel is routed to rear-panel I/O connector J5, providing an optional transition board (such as the ZT 4807 Rear-Panel Transition Board) signals for up to two external IDE devices. ...
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IDE Interface 5.3 I/O Mapping The I/O map for the IDE interface varies depending on the mode of operation (see Address Map” on page interface uses the PC-AT legacy addresses of 1F0h-1F7h, with 3F6h and interrupt IRQ14 for the primary ...
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Watchdog Timer This chapter explains the operation of the ZT 5524 / MPCBL5524 Watchdog Timer. It provides an overview of watchdog operation and features, as well as sample code to help you learn how the Watchdog Timer works with applications. ...
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Watchdog Timer 6.2 Power-Up Initialization The Watchdog Timer’s programmable logic is initialized only at power-up. This ensures that the NMI, RST, NMI ENABLE, and RESET ENABLE status and control bits power up to unasserted states, allowing the BIOS or user ...
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Setting the Terminal Count The terminal count determines how long the watchdog waits for a strobe before resetting the hardware. C code for setting the terminal count might look like the following: #define WD_CSR_IO_ADDRESS #define WD_T_COUNT_MASK #define WD_500MS_T_COUNT #define ...
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Watchdog Timer 6.4.2.1 Chaining the ISRs Save the original NMI ISR vector so that it can be invoked from the new watchdog NMI ISR. Alter the interrupt vector table so that the NMI ISR vector is overwritten with a vector ...
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NMI Handler Because the NMI may have originated from another source such as a RAM Error Correction Code (ECC) error, the NMI handler cannot assume that the NMI occurred due to a watchdog time out. Therefore, the NMI handler ...
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BIOS Recovery BIOS Recovery The ZT 5524 / MPCBL5524 provides on-board flash memory containing the system BIOS. The flash device is divided into eight pages mapped into a window in extended memory (FFF80000h–FFFFFFFFh). The BIOS occupies 512 ...
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Forcing a Boot from the BIOS Recovery Module To force a boot from the BIOS recovery module: 1. Remove the board from the enclosure. 2. Close switch SW4-2 to boot from the BIOS Recovery Module. 3. Make sure flash ...
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System Monitoring and Alarms System Monitoring and Alarms The ZT 5524 / MPCBL5524 performs system monitoring and alarming functions using the flexible, industry standard, Intelligent Platform Management Interface (IPMI). The ZT 5524 / MPCBL5524 comes equipped with an on-board Baseboard ...
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Table 14. SMBus Address Map (Sheet Gigabit Ethernet Channels A/B BMC SCL4 ADM1026 RPIO FRU Device Mezzanine Card FRU Device Mezzanine RPIO Card FRU Device ADM1026 Mezzanine 10/100 Ethernet Controller C ® Intel NetStructure ZT 5524 / ...
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Specifications Specifications This appendix describes the electrical, environmental, and mechanical specifications of the ZT 5524 / MPCBL5524. It includes illustrations of the board dimensions and connector locations, as well as connector descriptions and pinout tables. A.1 Electrical and Environmental Specifications ...
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A.1.1.1 Operating Temperature Operating temperature is processor dependent. The operating temperature range is 0° 45° C. The ZT 5524 / MPCBL5524 comes from the factory with an integrated heat sink for cooling the processor. The heat sink requires ...
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Specifications A.3 Mechanical Specifications This section includes the following mechanical specifications for the ZT 5524 / MPCBL5524: • Board dimensions and weight • Connectors (including connector locations, descriptions, and pinouts) A.3.1 Board Dimensions and Weight The ZT 5524 / MPCBL5524 ...
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A.3.2 ZT 5524 / MPCBL5524 Connectors As shown in the Figure 9, “Connector Locations” on page several connectors to interface with application-specific devices. A brief description of each connector is given in the “Connector Assignments” table. A detailed description and ...
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Specifications Figure 9. Connector Locations J6 - USB J12 - Hot Swap Ejector Switch J1 CompactPCI Bus Figure 10. Backplane Connectors Pin Locations ® 60 Intel NetStructure ZT 5524 / MPCBL5524 High-Performance System Master Processor Board TPS J8 - Keyboard/Mouse ...
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A.3.2.1 J1 (CompactPCI Bus Connector 125-pin mm, female 32-bit CompactPCI connector. Rows 12-14 are used for connector keying. See the “J1 CompactPCI Bus Connector Pinout” table for pin definitions and Figure 10, “Backplane ...
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Specifications A.3.2.2 J2 (CompactPCI Bus Connector 110-pin mm, right-angle female 64-bit CompactPCI connector. See the “J2 CompactPCI Bus Connector Pinout” table for pin definitions and Connectors Pin Locations” on page 60 Table 20. ...
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A.3.2.3 J3 (Rear-Panel Gigabit Ethernet Connector 95-pin mm, female connector providing rear-panel access to Ethernet A and Ethernet B. See the “J3 Rear-Panel Gigabit Ethernet Connector Pinout” table for pin definitions and Figure ...
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Specifications • SMBus • Power and Ground See the “J5 Rear-Panel User I/O Connector Pinout” table for pin definitions and “Backplane Connectors Pin Locations” on page 60 Table 22. J5 Rear-Panel User I/O Connector Pinout Pin # A 22 USB0+ ...
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A.3.2.5 J6 (USB Connectors 4-pin, Port 0 USB Interface connector on the ZT 5524 / MPCBL5524’s faceplate. USB (Port 1) is directed out rear-panel I/O connector J5. See the “J6 USB Connector Pinout” table for pin definitions. ...
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Specifications A.3.2.7 J8 (Keyboard/Mouse Connector 6-pin, right angle, DIN connector providing for standard PS/2 style keyboard and mouse device connection on the ZT 5524 / MPCBL5524’s faceplate. For a diagram of the faceplate, see Figure 1, “ZT ...
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A.3.2.9 J10 (Video Interface) J10 is an HD15, 15-pin, female, D-shell connector providing an interface for VGA signals on the ZT 5524 / MPCBL5524’s faceplate. See the following table for pin definitions. Table 27. J10 Video Interface Pinout Pin# Signal ...
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Specifications Table 29. J12 Hot Swap Ejector Switch Connector Pinout Pin# Function 1 Common 2 Latched 3 Unlatched A.3.2.12 J13 (SDRAM Connector) J13 is a 168-pin, right angle connector that accommodates a standard 3.3 V registered dual inline memory module ...
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Table 30. J17 I/O Mezzanine Interface Connector Pinout (Sheet Signal Name n 20 B1_PAD24 21 B1_PAD23 22 B1_PAD22 23 B1_PAD21 24 B1_PAD20 25 IOXB_IDSEL 26 IOXA_IDSEL 27 B1_PAD19 28 B1_PAD18 29 MEZ_INTC- 30 B1_PAD16 31 B1_PAD17 ...
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Specifications A.3.2.14 J18 (ISP Programming Interface) J18 is a dual-row 10-pin, female (.079 in) center, vertical header providing an on-board ISP interface. See the following table for pin definitions. Table 31. J18 ISP Programming Interface Pin Signal Name ...
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Table 32. J19 EIDE Interface Pinout (Sheet Pin# Signal 19 GND PDREQ- 22 GND 23 PDIOW- 24 GND 25 PDIOR- 26 GND 27 PDIORDY 28 CSEL 29 PDACK- 30 GND 31 IRQ14 1 32 ...
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System Registers System Registers The ZT 5524 / MPCBL5524 provides several system registers to control and monitor a variety of functions on the ZT 5524 / MPCBL5524. Normally, only the system BIOS uses these registers, but they are documented here ...
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Table 34. Flash Control Bit Descriptions Bit BIOS Recovery Module Override Bit This bit supersedes the Boot Source switch (SW4-2, see Override bit is set to 1, then the Boot Source switch has no affect on the boot device, and ...
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System Registers Table 35. Watchdog Bit Descriptions (Sheet Bit Stage 2 Monitor (Reset Monitor) Monitors the second stage (Reset) timer status. Read Value: 0= Watchdog has not timed out since power up or since this bit was ...
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Table 35. Watchdog Bit Descriptions (Sheet Stage 1 Enable Enables NMI activation on timeout. Read Value: 0= Disabled 1= Enable NMI activation on timeout Write Value: 0= Disable NMI operation of the watchdog. When the watchdog times ...
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System Registers B.1.4 ENUM, WD NMI Status, PWR Supply Status (E1h) I/O Address Default Value Size Attribute Table 37. ENUM, WD NMI Status Bit Descriptions Bit 7 WD NMI Status ENUM-. This bit reports that a hot swappable peripheral card ...
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Table 39. Switch Monitors Bit Descriptions Bit Flash Write-Protect Status. This bit corresponds to the status of Flash Write Protect/Write Enable 7 switch SW4-1 (see means that the flash is not write-protected by SW4-1. Boot Source Monitoring. This bit allows ...
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System Registers B.1.8 Video/LED Control (E5h) Address Offset Default Value Size Attribute Table 41. Video/LED Control Bit Descriptions Bit 7:5 Reserved. These bits are reserved and should not be modified by the user. Video Front/Rear Selection. This bit toggles video ...
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B.1.10 HCDATA - Host Control Function Data (E7h) I/O Address Reset Default Value Size Attribute Table 43. HCDATA Bit Description Bit This register provides access to the Host Control Function Registers. The particular register accessed 7:0 is determined by the ...
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System Registers For example, to read the data in HCC, first write XXh, to HCINDEX. Then read HCDATA. The contents of HCC are mapped into HCDATA. HCINDEX and HCDATA registers are located on page 78. Table 45. Host Control Function ...
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B.2.2 CICAC- CompactPCI Interface Controller A Command HCINDEX Reset Default Value Size Attribute Note: Writes to this register must be made with extreme caution. In the interest of security, an unlock bit is included in the CICAS Register. That bit ...
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System Registers B.2.3 CICBS- CompactPCI Interface Controller B Status HCINDEX Reset Default Value Size Attribute Table 48. CICBS Bit Descriptions Bit 7 CIC B Present. If this bit is set, there is a CIC B present. Segment Reset. If set, ...
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Table 49. CICBC Bit Descriptions Bit 7:6 Reserved. Reserved for future use. Arbiter Enable. Read the Arbiter is enabled 0 = the Arbiter is locked or disabled Write: 5 When in Drone mode, this bit is cannot be ...
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Reset Reset This appendix discusses the various reset types and reset sources on the ZT 5524 / MPCBL5524. Because many embedded systems have different requirements for board reset functions, the incorporation of this sub-system on the ZT 5524 / MPCBL5524 ...
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CompactPCI bus push-button reset signal, PRST# (J2-C17) • PBRST- (J3-A4) generated by an RPIO transition board (e.g., the ZT 4807 Rear-Panel Transition Board’s push button-switch SW2 Note: For a diagram of the faceplate, see C.1.3 NMI Sources Abort Push ...
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Thermal Considerations Thermal Considerations This appendix describes the thermal requirements to reliably operate a ZT 5524 / MPCBL5524 processor board with a Pentium III processor. D.1 Thermal Requirements The maximum processor core temperature allowed by the Pentium III processors on ...
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Data Sheet Reference This appendix provides links to data sheets, standards, and specifications for the technology designed into the ZT 5524 / MPCBL5524. E.1 Chipset The ZT 5524 / MPCBL5524 incorporates the ServerWorks* Champion LE-T chipset. The Champion LE-T chipset ...
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Data Sheet Reference E.4 Intelligent Platform Management Interface (IPMI) See the Intel IPMI home page for information concerning the Intelligent Platform Management Interface, including the Intelligent Platform Management Interface v1.5 Specification and the Intelligent Platform Management Interface Implementer’s Guide: http://developer.intel.com/design/servers/ipmi/spec.htm ...
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E.8 Thermal Management For more information about the Analog Devices* ADM1026 Complete Thermal System Management Controller, see the manufacturer’s website at: http://products.analog.com/products/info.asp?product=ADM1026 E.9 User Documentation The latest Intel NetStructure ® product information and manuals are available on the Intel NetStructure ...
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Warranty Information Warranty Information F.1 Intel NetStructure Products Limited Warranty Intel warrants to the original owner that the product delivered in this package will be free from defects in material and workmanship for two (2) year(s) following the latter of: ...
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F.1.2 For the Americas Return Material Authorization (RMA) credit requests e-mail address: Direct Return Authorization (DRA) repair requests e-mail address: DRA on-line form: Intel Business Link (IBL): Telephone No.: 1-800-INTEL4U or 480-554-4904 Office Hours: Monday - Friday 0700-1700 MST Winter ...
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Warranty Information If the Customer Support Group verifies that the product is defective, they will have the Direct Return Authorization/Return Material Authorization Department issue you a DRA/RMA number to place on the outer package of the product. Intel cannot accept ...
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Customer Support This appendix offers technical and sales assistance information for this product, and information on returning an Intel NetStructure product for service. G.1 Technical Support and Return for Service Assistance For all product returns and support issues, please contact ...
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Agency Approvals Agency Approvals This appendix presents agency approval and certification information for the ZT 5524 / MPCBL5524 Processor Board. H.1 UL 1950 Certification Underwriters Laboratories, Inc.* Safety: H.2 CE Certification The ZT 5524 / MPCBL5524 meets the intent of ...
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H.2.0.3 BELLCORE GR-1089-CORE Sect. 2 Sect. 3.2.2 Sect. 3.2.3 Sect. 3.3.1 Sect. 3.3.3 H.2.0.4 Low Voltage Directive 73/23/EEC UL 1950/EN 60950 H.3 FCC Regulatory Information Regulatory information: Federal Communications Commission* (FCC) (USA only). Caution: This equipment has been tested and ...