LTM9005IV-AA#PBF Linear Technology, LTM9005IV-AA#PBF Datasheet - Page 18

• Manufacturer Part Number: LTM9005IV-AA#PBF
• Manufacturer: Linear Technology

Specifications of LTM9005IV-AA#PBF

• Lead Free Status / RoHS Status: Compliant

LTM9005
applicaTions inForMaTion
Minimum gain is achieved by sinking approximately 10mA
from the GAIN pin. If the gain is to be adjusted as part of
an active control loop then the circuit in Figure 11 can be
used. See the Typical Performance Characteristics for the
transfer function.
The DAC used to control GAIN will contribute a non-neg-
ligible amount of voltage noise. (Text to come—discuss
further and provide noise analysis.)
In some applications it may be sufficient to permanently
set the gain to a fixed level. This simplifies the circuitry as
a fixed resistor to ground can be implemented.
DIGITAL OUTPUTS
Table 3 shows the relationship between the analog input
voltage, the digital data bits, and the overflow bit.
Table 3. Output Codes vs Input Voltage, LTM9005-AA
Overvoltage
Maximum
Minimum
Undervoltage
18
(SENSE = V
INPUT
DD
Figure 11. Automatic Gain Control Circuit
)
LTM9005
OF
1
0
0
0
0
0
0
0
0
1
49.9Ω
11 1111 1111 1111
11 1111 1111 1111
11 1111 1111 1110
10 0000 0000 0001
10 0000 0000 0000
01 1111 1111 1111
01 1111 1111 1110
00 0000 0000 0001
00 0000 0000 0000
00 0000 0000 0000
GAIN
(OFFSET BINARY)
V
CC1
D13 – D0
TBDΩ
9005 F11
(2’S COMPLEMENT)
01 1111 1111 1111
01 1111 1111 1111
01 1111 1111 1110
00 0000 0000 0001
00 0000 0000 0000
11 1111 1111 1111
11 1111 1111 1110
10 0000 0000 0001
10 0000 0000 0000
10 0000 0000 0000
D13 – D0
Digital Output Modes
Figure 12 shows an equivalent circuit for a single output
buffer. Each buffer is powered by OV
from the ADC power and ground. The additional N-channel
transistor in the output driver allows operation down to
low voltages. The internal resistor in series with the output
makes the output appear as 50Ω to external circuitry and
may eliminate the need for external damping resistors.
As with all high speed/high resolution converters the digital
output loading can affect the performance. The digital
outputs of the ADC should drive a minimal capacitive load
to avoid possible interaction between the digital outputs
and sensitive input circuitry. For full speed operation, the
capacitive load should be kept under 10pF .
Lower OV
from the digital outputs.
Data Format
Using the MODE pin, the ADC parallel digital output can
be selected for offset binary or 2’s complement format.
Connecting MODE to GND or 1/3V
output format. Connecting MODE to 2/3V
2’s complement output format. An external resistive divider
can be used to set the 1/3V
Table 5 shows the logic states for the MODE pin.
LATCH
FROM
DATA
OE
PREDRIVER
LOGIC
DD
V
DD
voltages will also help reduce interference
Figure 12. Digital Output Buffer
V
DD
DD
DD
or 2/3V
DD
selects straight binary
OV
and OGND, isolated
DD
LTM9005
DD
DD
43Ω
or V
9005 F12
logic values.
DD
OV
OGND
DD
selects
TYPICAL
DATA
OUTPUT
0.5V
TO 3.6V
9005p