SCN68681E1N40 NXP Semiconductors, SCN68681E1N40 Datasheet - Page 18

• Manufacturer Part Number: SCN68681E1N40
• Manufacturer: NXP Semiconductors

Specifications of SCN68681E1N40

• Transmitter And Receiver Fifo Counter: No
• Operating Supply Voltage (typ): 5V
• Package Type: PDIP
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Mounting: Through Hole
• Pin Count: 40
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Number Of Channels: 2
• Lead Free Status / RoHS Status: Compliant

continues counting past the terminal count until stopped by the CPU.
count becomes effective only on the next start counter commands. If
Philips Semiconductors
In the counter mode, the C/T counts down the number of pulses
loaded into CTUR and CTLR by the CPU. Counting begins upon
receipt of a start counter command. Upon reaching terminal count
0000
If OP3 is programmed to be the output of the C/T, the output
remains HIGH until terminal count is reached, at which time it goes
LOW. The output returns to the HIGH state and ISR[3] is cleared
when the counter is stopped by a stop counter command. The CPU
may change the values of CTUR and CTLR at any time, but the new
new values have not been loaded, the previous count values are
preserved and used for the next count cycle
2004 Mar 02
Dual asynchronous receiver/transmitter (DUART)
16
, the counter ready interrupt bit (ISR[3]) is set. The counter
18
In the counter mode, the current value of the upper and lower 8 bits
of the counter (CTU, CTL) may be read by the CPU. It is
recommended that the counter be stopped when reading to prevent
potential problems which may occur if a carry from the lower 8 bits
to the upper 8 bits occurs between the times that both halves of the
counter are read. However, note that a subsequent start counter
command will cause the counter to begin a new count cycle using
the values in CTUR and CTLR.
IVR – Interrupt Vector Register
This register contains the interrupt vector. The register is initialized
to H‘0F’ by RESET. The contents of the register are placed on the
data bus when the DUART responds to a valid interrupt
acknowledge cycle.
SCN68681
Product data