RU82566DM Q 881 Intel, RU82566DM Q 881 Datasheet - Page 18

• Manufacturer Part Number: RU82566DM Q 881
• Manufacturer: Intel

Specifications of RU82566DM Q 881

• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 81
• Lead Free Status / RoHS Status: Compliant

1.4.21
1.4.22
1.4.23
1.4.24
18
Reserved Word 19h
This field is loaded to bits 15:0 of the FEXTNVM register.
Reserved Word 1Ah
This word is loaded to bits 31:16 of the FEXTNVM register.
Reserved Word 1Bh
Reserved Word 1Ch
1. 82567LM only.
1. These bits are reserved and should be set to 10F5h for the 82567LM.
15:0
15:7
6
5:2
1
0
15:0
15:0
Bit
Bit
Bit
Bit
Reserved
Reserved
Reserved
Reserved
Reserved
APM Enable
Reserved
Reserved
Name
Name
Name
Name
2B00h
0B00
00h
1b
00h
1b
1b
Default
Default
00h
BAADh
10F5h
Default
Default
1
1
See FEXTNVM register definition for the breakdown of the bits.
Reserved
Reserved
Reserved
Reserved
APM Enable
Initial value of Advanced Power Management Wake Up Enable in
the Wake Up Control (WUC.APME) register. Also mapped to
CTRL[6]. When the APM Enable bit is set, both the PHY and MAC
should be initialized to a functional state following power up. This
bit is loaded also to the FEXTNVM register (bit 16); however, the
bit in the FEXTNVM does not impact device functionality.
1b = Advanced power management enabled.
0b = Advanced power management disabled.
These bits are reserved and should be set to 00h.
These bits are reserved and should be set to BAADh for the
82566 and 82562V.
NVM Information Guide—ICH9/82566/82567LM/82567V
Description
Description
Description
Description