CYNSE70032-66BGI Cypress Semiconductor Corp, CYNSE70032-66BGI Datasheet - Page 21

• Manufacturer Part Number: CYNSE70032-66BGI
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE70032-66BGI

• Operating Supply Voltage (typ): 1.8V
• Operating Supply Voltage (min): 1.7V
• Operating Supply Voltage (max): 1.9V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Table 12-5. Read Address Format for Internal Registers
The read operation lasts 4 + 2n CLK cycles (where n is the number of accesses in the burst specified by the BLEN field of the
RBURREG) in the sequence shown below. This operation assumes that the host ASIC has programmed the RBURREG with the
ADR and the BLEN before initiating a burst Read command.
Cycles 4 and 5 repeat for each additional access until all the accesses specified in the BLEN field of the RBURREG are complete.
On the last transfer, the CYNSE70032 device drives the EOT signal high.
At the termination of cycle (4 + 2n), the selected device floats the ACK line to a three-state condition. The burst Read instruction
is complete, and a new operation can begin. Table 12-6 describes the Read address format for data and mask arrays for burst
Read operations.
Table 12-6. Read Address Format for Data and Mask Arrays
12.4
The Write command can be a single Write of a data array, mask array, register, or an external SRAM location (CMD[2] = 0). It
can also be a burst Write (CMD[2] = 1) using an internal auto-incrementing address register (WBURADR) of the data or mask
array locations. A single-location Write is a three-cycle operation as shown in Figure 12-3. The burst Write adds one extra cycle
for each successive location Write.
Document #: 38-02042 Rev. *E
DQ[67:26] DQ[25:21]
• Cycle 1: The host ASIC applies the Read instruction on CMD[1:0] (CMD[2] = 1) using CMDV = 1 and the address supplied
• Cycle 2: The host ASIC floats DQ[67:0] to a three-state condition.
• Cycle 3: The host ASIC keeps DQ[67:0] in a three-state condition.
• Cycle 4: The selected device starts to drive the DQ[67:0] bus, and drives ACK and EOT from Z to low.
• Cycle 5: The selected device drives the Read data from the addressed location on the DQ[67:0] bus and drives the ACK signal
• Cycle (4 + 2n): The selected device drives the DQ[67:0] to a three-state condition, and drives the ACK and EOT signals low.
Reserved
Reserved
on the DQ bus as shown in Table 12-6. The host ASIC selects the CYNSE70032 device where ID[4:0] matches the DQ[25:21]
lines. If DQ[25:21] = 11111, the host ASIC selects the CYNSE70032 device with the LDEV bit set.
high.
DQ[67:26]
Reserved
Write Command
ID
ID
CMD[1:0]
CMD[8:2]
CLK2X
PHS_L
CMDV
01: Mask Array Reserved Do not care. These fifteen bits come from the internal RBURADR, which
ACK
EOT
00: Data Array Reserved Do not care. These fifteen bits come from the internal RBURADR, which
DQ
DQ[20:19]
Figure 12-2. Burst Read of the Data and Mask Arrays (BLEN = 4)
DQ[25:21]
ID
Address
cycle
Read
A B
1
DQ[18:14]
cycle
2
cycle
3
cycle
increments for each access.
increments for each access.
FF
4
11: Register
DQ[20:19]
cycle
Data0
5
cycle
6
FF
cycle
Data1
7
cycle
8
FF
cycle
Data2
9
Reserved
DQ[18:6]
cycle
10
FF
DQ[13:0]
cycle
11
Data3
cycle
12
Register Address
CYNSE70032
DQ[5:0]
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