CYNSE70032-66BGI Cypress Semiconductor Corp, CYNSE70032-66BGI Datasheet
CYNSE70032-66BGI
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CYNSE70032-66BGI Summary of contents
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... CYNSE70032 Network Search Engine Cypress Semiconductor Corporation Document #: 38-02042 Rev. *E • 3901 North First Street • CYNSE70032 , San Jose CA 95134 • 408-943-2600 Revised May 5, 2003 ...
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... Search on Tables Configured as ×136 Using a Single CYNSE70032 Device ........... 45 13.5 136-bit Search on Tables Configured as ×136 Using up to Eight CYNSE70032 Devices ..... 48 13.6 136-bit Search on Tables Configured as ×136 using CYNSE70032 Devices ......... 54 13.7 272-bit Search on Tables Configured as ×272 using a Single CYNSE70032 Device ........... 69 13.8 272-bit Search on Tables Configured as ×272 and Using up to Eight CYNSE70032 Devices .................................................................................................. 71 13.9 272-bit Search on Tables Configured as × ...
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... APPLICATION .......................................................................................................................... 114 18.0 JTAG (1149.1) TESTING .......................................................................................................... 115 19.0 ELECTRICAL SPECIFICATIONS ............................................................................................. 116 20.0 AC TIMING WAVEFORMS ....................................................................................................... 117 21.0 PINOUT DESCRIPTIONS AND PACKAGE DIAGRAMS ......................................................... 120 22.0 ORDERING INFORMATION ..................................................................................................... 124 23.0 PACKAGE DIAGRAMS ............................................................................................................ 124 Document #: 38-02042 Rev. *E TABLE OF CONTENTS (continued) CYNSE70032 Page 3 of 126 ...
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... Figure 7-2. Addressing the Global Mask Register Array ..................................................................... 14 Figure 10-1. CYNSE70032 Database Width Configuration ................................................................. 17 Figure 10-2. Multiwidth Database Configurations ................................................................................ 18 Figure 11-1. Addressing CYNSE70032 Data and Mask Arrays .......................................................... 18 Figure 12-1. Single-Location Read Cycle Timing ................................................................................ 20 Figure 12-2. Burst Read of the Data and Mask Arrays (BLEN = 4) ..................................................... 21 Figure 12-3 ...
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... Figure 15-4. SRAM Read Timing for Device Number Block of Eight Devices ......................... 103 Figure 15-5. Table of 31 Devices Made of Four Blocks ..................................................................... 104 Figure 15-6. SRAM Read Through Device Number Bank of 31 Devices (Device Number 0 Timing) .................................................................................................................. 105 Document #: 38-02042 Rev. *E LIST OF FIGURES (continued) CYNSE70032 Page 5 of 126 ...
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... Figure 15-12. Table of 31 Devices (Four Blocks) .............................................................................. 111 Figure 15-13. SRAM Write Through Device Number Bank of 31 Devices (Device 0 Timing) . 112 Figure 15-14. SRAM Write Through Device Number Bank of 31 CYNSE70032 Devices (Device Number 30 Timing) ................................................................................................................ 113 Figure 16-1. Power-up sequence ...................................................................................................... 114 Figure 17-1 ...
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... Table 13-25. SRAM Write Cycle Latency from Second Cycle of Learn Instruction ............................. 95 Table 15-1. SRAM Bus Address .......................................................................................................... 99 Table 18-1. Supported Operations .................................................................................................... 115 Table 19-1. DC Electrical Characteristics for CYNSE70032 .............................................................116 Table 19-2. Operating Conditions for CYNSE70032 ......................................................................... 116 Table 18-2. TAP Device ID Register ................................................................................................. 116 Document #: 38-02042 Rev. *E LIST OF TABLES ...
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... Table 19-3. Operating Range for CYNSE70032 ................................................................................ 117 Table 20-1. AC Timing Parameters with CLK2X ............................................................................... 117 Table 20-2. Test Conditions of CYNSE70032 ...................................................................................117 Table 21-1. Pinout Descriptions for Pinout Diagram ..........................................................................120 Table 22-1. Ordering Information ....................................................................................................... 124 Document #: 38-02042 Rev. *E LIST OF TABLES (continued) CYNSE70032 Page 8 of 126 ...
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... Associative Processing Technology™ (APT) and is designed high-performance, pipelined, synchronous, 16K-entry NSE. The CYNSE70032 database entry size can be 68, 136, or 272 bits. In the 68-bit entry mode, the size of the database is 16K entries. In the 136-bit mode, the size of the database is 8K entries, and in the 272-bit mode, the size of the database is 4K entries. ...
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... Compare/PIO Data Configurable as 16K 136 4K x 272 Data Array Configurable as 16K 136 4K x 272 Mask Array LHI[6:0] Arbitration BHI[2:0] Logic FULL FULO[1:0] CYNSE70032 TAP TAP Controller SADR[21:0] OE_L Pipeline and WE_L SRAM Control CE_L ALE_L LHO[1:0] BHO[2:0] SSF SSV Page 10 of 126 ...
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... ACK and EOT require a weak external pull-down such as 47K Document #: 38-02042 Rev. *E Master Clock. CYNSE70032 samples all the data and control pins on the positive edge of CLK2X. All signals are driven out of the device on the rising edge of CLK2X (when PHS_L is low). Phase. This signal runs at half the frequency of CLK2X and generates an internal clock from CLK2X. See Section 6.0, “ ...
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... LRAM bit set). Address Latch Enable. When this signal is low, the addresses are valid on the SRAM address bus database of multiple CYNSE70032s, the ALE_L of all cascaded devices must be connected. This signal is then driven by only one of the devices. ...
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... Clocks The CYNSE70032 device receives the CLK2X and PHS_L signals. It uses the PHS_L signal to divide CLK2X and generate an [3] internal clock (CLK ), as shown in Figure 6-1. The CYNSE70032 device uses CLK2X and CLK for internal operations. CLK2X PHS_L [4] CLK Figure 6-1. CYNSE70032 Clocks (CLK2X and PHS_L) 7 ...
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... SSF, and SSV signals in a three-state condition and forces the cascade interface output signals LHO[1:0] and BHO[2: also keeps the DQ bus in input mode. The purpose of this bit is to make sure that there are no bus contentions when the devices power up in the system. CYNSE70032 . In 68-bit Search and Note 0 ...
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... Last Device on the SRAM Bus. When set, this device is the last device on the SRAM bus in the depth-cascaded table and is the default driver for the SADR, CE_L, WE_L, and ALE_L signals. In cycles where no CYNSE70032 device (in a depth-cascaded table) drives these signals, the signals are driven as follows: SADR = 22’h3FFFFF, CE_L = 1, WE_L = 1, and ALE_L = 1. OE_L is always driven by the device for which this bit is set. Database Configuration. The device is divided internally into four partitions of 8K × ...
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... This is stored in the NFA register (see Table 9-4). If all the bits[ device are set to 1, the CYNSE70032 asserts FULO[1: For a 136-bit-configured quadrants, the LSB of the NFA register is always set to 0. The host ASIC must set both bit[0] and bit[68 136-bit word to either indicate full or empty status ...
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... NSE Architecture and Operation Overview The CYNSE70032 device consists of 16K × 68-bit storage cells referred to as data bits. There is a mask cell corresponding to each data cell. Figure 10-1 shows the three organizations of the device based on the value of the CFG bits in the command register ...
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... Figure 11-1. Addressing CYNSE70032 Data and Mask Arrays 12.0 Commands A master device such as an ASIC controller issues commands to the CYNSE70032 device using the command valid (CMDV) signal and the CMD bus. The following subsections describe the operation of the commands. 12.1 Command Codes The CYNSE70032 device implements four basic commands, shown in Table 12-1 ...
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... Commands and Command Parameters Table 12-2 lists the CMD bus fields that contain the CYNSE70032 command parameters and their respective cycles. Each command is described separately in the subsections that follow. Table 12-2. Command Parameters Command CYC 8 Read A SADR[21 Write A SADR[21 Search ...
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... Table 12-4 and Table 12-5. The host ASIC selects the CYNSE70032 device for which ID[4:0] matches the DQ[25:21] lines. If DQ[25:21] = 11111, the host ASIC selects the CYNSE70032 with the LDEV bit set. The host ASIC also supplies SADR[21:19] on CMD[8:6] in cycle A of the Read instruction if the Read is directed to the external SRAM. ...
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... Cycle 1: The host ASIC applies the Read instruction on CMD[1:0] (CMD[ using CMDV = 1 and the address supplied on the DQ bus as shown in Table 12-6. The host ASIC selects the CYNSE70032 device where ID[4:0] matches the DQ[25:21] lines. If DQ[25:21] = 11111, the host ASIC selects the CYNSE70032 device with the LDEV bit set. ...
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... Reserved If DQ[29 this field carries the address of the External SRAM location. If DQ[29 the SSR specified on SRAM DQ[28:26] is used to generate the address of the SRAM location: {SSR[13:2], SSR[1] | DQ[1], SSR[0] | DQ[0]}. DQ[20:19] DQ[18:6] 11: Register Reserved CYNSE70032 cycle 3 cycle 4 X DQ[13:0] [6] [6] [6] DQ[5:0] Register address Page 22 of 126 ...
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... The CYNSE70032 device writes the data on the DQ[67:0] bus only to the subfield that has the corresponding mask bit set the GMR that is specified by the index CMD[5:3] supplied in cycle 1. The CYNSE70032 device drives the EOT signal low from cycle 3 to cycle n; the CYNSE70032 device drives the EOT signal high in cycle specified in the BLEN field of the WBURREG). ...
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... Search on tables configured as ×272 using one device • 272-bit Search on tables configured as ×272 using up to eight devices • 272-bit Search on tables configured as ×272 using devices • Mixed-size searches on tables configured with different widths using an CYNSE70032. 13.1 68-bit Search on Tables Configured as Figure 13-1 shows the timing diagram for a Search command in a 68-bit-configured table (CFG = 00000000) consisting of a single device for one set of parameters: TLSZ = 00, HLAT = 000, LRAM = 1, and LDEV = 1 ...
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... The latency of SADR, CE_L, ALE_L, WE_L, SSV, and SSF from the 68-bit Search command cycle (which is two CLK2X cycles) is shown in Table 13-1. Document #: 38-02042 Rev LHI CYNSE70032 LHO[1] 67 GMR K 67 Location address 16383 CFG = 00000000 (68-bit configuration) Figure 13-3. ×68 Table with One Device CYNSE70032 SRAM LHO[ (First matching entry) Page 25 of 126 ...
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... Search on Tables Configured as ×68 Using up to Eight CYNSE70032 Devices The hardware diagram of the Search subsystem of eight devices is shown in Figure 13-4. The following are the parameters programmed into the eight devices. • First seven devices (devices 0–6): CFG = 00000000, TLSZ = 01, HLAT = 010, LRAM = 0, and LDEV = 0. ...
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... BHI[2:0] BHI[2:0] BHI[2:0] BHI[2:0] Figure 13-4. Hardware Diagram for a Table with Eight Devices Document #: 38-02042 Rev CYNSE70032 #0 LHO[ CYNSE70032 #1 LHO[ CYNSE70032 #2 LHO[1] BHI[2: CYNSE70032 #3 LHO[ CYNSE70032 # LHI LHI CYNSE70032 #5 LHO[ LHI CYNSE70032 #6 LHO[ LHI LHI CYNSE70032 #7 CYNSE70032 LHI LHO[ LHI LHO[0] ...
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... Note: Each bit in LHO[1:0] is the same logical signal. Figure 13-5. Timing Diagram for 68-bit Search Device Number 0 Document #: 38-02042 Rev. *E cycle cycle cycle cycle cycle cycle cycle Search1 Search3 Search2 Search4 CYNSE70032 cycle cycle cycle Search1 Search3 (This device (This device is the global is the global winner ...
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... Note: Each bit in LHO[1:0] is the same logical signal. Figure 13-6. Timing Diagram for 68-bit Search Device Number 1 Document #: 38-02042 Rev. *E cycle cycle cycle cycle cycle cycle cycle Search1 Search3 Search2 Search4 CYNSE70032 cycle cycle cycle Search1 Search3 (Miss on (Local but this device.) not global winner.) Search4 Search2 (Miss on (This device this device ...
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... The word K (presented on the DQ bus in both cycles A and B of Document #: 38-02042 Rev. *E cycle cycle cycle cycle cycle cycle cycle Search3 Search1 Search2 Search4 CYNSE70032 cycle cycle cycle Search1 Search3 (Miss on (Local but this device.) not global winner ...
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... The hardware diagram of the Search subsystem of 31 devices is shown in Figure 13-9. Each of the four blocks in the diagram represents eight CYNSE70032 devices (except the last, which has seven devices). The diagram for a block of eight devices is shown in Figure 13-10. The following are the parameters that are programmed into the 31 devices. ...
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... BHO[1] BHI[2] BHI[1] Block of 8 CYNSE70032s Block 1 (devices 8–15) BHO[2] BHO[1] BHI[2] BHI[1] Block of 8 CYNSE70032s Block 2 (devices 16–23) BHO[2] BHO[1] BHI[2] BHI[1] Block of 7 CYNSE70032s Block 3 (devices 24–30) BHO[2] BHO[1] CYNSE70032 3 4 Miss Miss Hit Miss Hit Miss Miss Miss ...
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... Figure 13-10. Hardware Diagram for a Block Eight Devices Document #: 38-02042 Rev LHI CYNSE70032 #0 LHO[ LHI CYNSE70032 #1 LHO[ LHI CYNSE70032 # LHI CYNSE70032 #3 LHO[ CYNSE70032 #4 LHI LHO[ LHI LHI CYNSE70032 #5 LHO[ LHI LHI CYNSE70032 #6 LHO[ LHI LHI CYNSE70032 #7 LHO[1] LHO[0] CYNSE70032 LHO[ LHO[ LHO[ BHO[0] ...
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... Figure 13-11. Timing Diagram for Each Device in Block Number 0 (Miss on Each Device) Document #: 38-02042 Rev. *E cycle cycle cycle cycle cycle cycle cycle Search3 Search1 Search2 Search4 CYNSE70032 cycle cycle cycle Search1 Search3 (Miss on (Miss on this device.) this device.) Search2 Search4 (Miss on (Miss on this device.) this device.) Page 34 of 126 ...
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... Figure 13-12. Timing Diagram for Each Device Above the Winning Device in Block Number 1 Document #: 38-02042 Rev. *E cycle cycle cycle cycle cycle cycle cycle Search3 Search1 Search2 Search4 CYNSE70032 cycle cycle cycle Search1 Search3 (Miss on (Miss on this device.) this device.) Search2 Search4 (Miss on (Miss on this device.) this device.) Page 35 of 126 ...
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... Figure 13-13. Timing Diagram for Globally Winning Device in Block Number 1 Document #: 38-02042 Rev. *E cycle cycle cycle cycle cycle cycle cycle Search3 Search1 Search2 Search4 CYNSE70032 cycle cycle cycle Search1 Search3 (Miss on (This device is this device.) global winner.) Search2 Search4 (Miss on (Miss on this device.) this device.) Page 36 of 126 ...
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... Figure 13-14. Timing Diagram for Devices Below the Winning Device in Block Number 1 Document #: 38-02042 Rev. *E cycle cycle cycle cycle cycle cycle cycle Search3 Search1 Search2 Search4 CYNSE70032 cycle cycle cycle Search1 Search3 (Miss on (Miss on this device.) this device.) Search2 Search4 (Miss on (Miss on this device.) this device.) Page 37 of 126 ...
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... Figure 13-15. Timing Diagram for Devices Above the Winning Device in Block Number 2 Document #: 38-02042 Rev. *E cycle cycle cycle cycle cycle cycle cycle Search3 Search1 Search2 Search4 CYNSE70032 cycle cycle cycle Search1 Search3 (Miss on (Miss on this device.) this device.) Search2 Search4 (Miss on (Miss on this device.) this device.) Page 38 of 126 ...
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... Figure 13-16. Timing Diagram for Globally Winning Device in Block Number 2 Document #: 38-02042 Rev. *E cycle cycle cycle cycle cycle cycle cycle Search1 Search3 Search2 Search4 CYNSE70032 cycle cycle cycle Search1 Search3 (Miss on (Hit but not this device.) winner.) Search2 Search4 (Miss on (Global this device ...
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... Figure 13-17. Timing Diagram for Devices Below the Winning Device in Block Number 2 Document #: 38-02042 Rev. *E cycle cycle cycle cycle cycle cycle cycle Search3 Search1 Search2 Search4 this device.) CYNSE70032 cycle cycle cycle Search1 Search3 (Miss on (Miss on this device.) Search2 Search4 (Miss on (Miss on this device.) this device.) Page 40 of 126 ...
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... Figure 13-18. Timing Diagram for Devices Above the Winning Device in Block Number 3 Document #: 38-02042 Rev. *E cycle cycle cycle cycle cycle cycle cycle Search1 Search3 Search2 Search4 CYNSE70032 cycle cycle cycle Search1 Search3 (Miss on (Miss on this device.) this device.) Search2 Search4 (Miss on (Miss on this device.) this device.) Page 41 of 126 ...
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... Note: Each bit in LHO[1:0] is the same logical signal. Figure 13-19. Timing Diagram for Globally Winning Device in Block Number 3 Document #: 38-02042 Rev. *E cycle cycle cycle cycle cycle cycle cycle Search3 Search1 Search2 Search4 CYNSE70032 cycle cycle cycle Search1 Search3 (Global (Miss on winner.) this device.) Search2 Search4 (Hit but not (Miss on global winner ...
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... Document #: 38-02042 Rev. *E cycle cycle cycle cycle cycle cycle Search3 Search1 Search2 Search4 (Except the Last Device [Device Number 30]) CYNSE70032 cycle cycle cycle cycle Search1 Search3 (Miss on (Miss on this device.) this device.) Search2 Search4 (Miss on (Miss on this device.) this device.) Page 43 of 126 ...
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... Document #: 38-02042 Rev. *E cycle cycle cycle cycle cycle cycle Search3 Search1 Search2 Search4 (Hit on some device above.) (Device Number 30 in Depth-Cascaded Table) CYNSE70032 cycle cycle cycle cycle Search1 Search3 (Hit on some device above.) Search2 Search4 (Hit on some (Global miss; device above.) this device default driver ...
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... Search on Tables Configured as ×136 Using a Single CYNSE70032 Device Figure 13-23 shows the timing diagram for a Search command in the 136-bit-configured table (CFG = 01010101) consisting of a single device for one set of parameters: TLSZ = 00, HLAT = 001, LRAM = 1, LDEV = 1. The hardware diagram for this Search subsystem is shown in Figure 13-24 ...
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... SSR[0:7]). The DQ[67:0] is driven with 68-bit data ([67:0]), compared to all odd locations. Document #: 38-02042 Rev. *E cycle cycle cycle cycle cycle cycle Search1 Search3 Search2 Search4 CYNSE70032 LHO[1] CYNSE70032 cycle cycle cycle cycle Search1 Search3 Hit Hit Search2 Search4 Miss Miss LHI ...
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... L 16382 CFG = 01010101 (136-bit configuration) Figure 13-25. ×136 Table with One Device Max Table Size 8K × 136 bits 64K × 136 bits 248K × 136 bits CYNSE70032 . The matching address is always going (First matching entry) Latency in CLK Cycles Number of CLK Cycles ...
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... Search on Tables Configured as ×136 Using up to Eight CYNSE70032 Devices The hardware diagram of the Search subsystem of eight devices is shown in Figure 13-26. The following are parameters programmed into the eight devices. • First seven devices (devices 0–6): CFG = 01010101, TLSZ = 01, HLAT = 010, LRAM = 0, and LDEV = 0. ...
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... BHI[2:0] BHI[2:0] BHI[2:0] BHI[2:0] Figure 13-26. Hardware Diagram for a Table with Eight Devices Document #: 38-02042 Rev CYNSE70032 #0 LHO[ CYNSE70032 #1 LHO[ CYNSE70032 #2 LHO[1] BHI[2: CYNSE70032 #3 LHO[ CYNSE70032 # LHI LHI CYNSE70032 #5 LHO[ LHI CYNSE70032 #6 LHO[ LHI LHI CYNSE70032 #7 CYNSE70032 LHI LHO[ LHI LHO[0] ...
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... Figure 13-27. Timing Diagram for 136-bit Search Device Number 0 Document #: 38-02042 Rev. *E cycle cycle cycle cycle cycle cycle cycle Search3 Search1 Search2 Search4 (This device is global winner.) CYNSE70032 cycle cycle cycle Search1 Search3 (This device is global winner.) Search4 Search2 (Miss on (Miss on this device ...
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... Figure 13-28. Timing Diagram for 136-bit Search Device Number 1 Document #: 38-02042 Rev. *E cycle cycle cycle cycle cycle cycle cycle Search1 Search3 Search2 Search4 CYNSE70032 cycle cycle cycle Search1 Search3 (Miss (Local but not on this global winner.) device.) Search4 Search2 (Miss This device on this is global winner ...
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... GMR Index in the command’s cycle A. Document #: 38-02042 Rev. *E cycle cycle cycle cycle cycle cycle cycle Search3 Search1 Search2 Search4 CYNSE70032 cycle cycle cycle Search3 Search1 (Local but not (Miss on global winner.) this device.) Search4 Search2 (Miss on (Global winner ...
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... Location address 131070 devices (136-bit configuration) Figure 13-30. ×136 Table with Eight Devices Max Table Size 8K × 136 bits 64K × 136 bits 248K × 136 bits Number of CLK Cycles CYNSE70032 0 Odd (First matching entry) CFG = 01010101 Latency in CLK Cycles ...
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... The hardware diagram of the Search subsystem of 31 devices is shown in Figure 13-31. Each of the four blocks in the diagram represents a block of eight CYNSE70032 devices (except the last, which has seven devices). The diagram for a block of eight devices is shown in Figure 13-32. The following are the parameters programmed into the 31 devices. ...
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... BHI[2] BHI[1] Block of 8 CYNSE70032s Block 1 (devices 8–15) BHO[2] BHO[1] BHI[2] BHI[1] Block of 8 CYNSE70032s Block 2 (devices 16–23) BHO[2] BHO[1] BHI[2] BHI[1] Block of 7 CYNSE70032s Block 3 (devices 24–30) BHO[2] BHO[1] CYNSE70032 BHI[0] GND SRAM BHO[0] BHI[0] GND BHO[0] GND BHI[0] BHO[0] ...
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... BHI[2:0] BHI[2:0] BHI[2:0] BHI[2:0] 3 Figure 13-32. Hardware Diagram for a Block Eight Devices Document #: 38-02042 Rev CYNSE70032 #0 LHO[ CYNSE70032 #1 LHO[ CYNSE70032 #2 LHO[ CYNSE70032 # CYNSE70032 #4 LHO[ LHI LHI CYNSE70032 #5 LHO[ LHI LHI CYNSE70032 #6 LHO[ LHI LHI CYNSE70032 #7 CYNSE70032 LHI LHO[ LHI LHO[ LHI ...
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... Figure 13-33. Timing Diagram for Each Device in Block Number 0 (Miss on Each Device) Document #: 38-02042 Rev. *E cycle cycle cycle cycle cycle cycle cycle Search1 Search3 Search2 Search4 CYNSE70032 cycle cycle cycle Search1 Search3 (Miss on (Miss on this device.) this device.) Search2 Search4 (Miss on (Miss on this device.) this device.) Page 57 of 126 ...
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... Figure 13-34. Timing Diagram for Each Device Above the Winning Device in Block Number 1 Document #: 38-02042 Rev. *E cycle cycle cycle cycle cycle cycle cycle Search3 Search1 Search2 Search4 CYNSE70032 cycle cycle cycle Search1 Search3 (Miss on (Miss on this device.) this device.) Search2 Search4 (Miss on (Miss on this device.) this device.) Page 58 of 126 ...
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... Figure 13-35. Timing Diagram for Globally Winning Device in Block Number 1 Document #: 38-02042 Rev. *E cycle cycle cycle cycle cycle cycle cycle Search3 Search1 Search2 Search4 CYNSE70032 cycle cycle cycle Search1 Search3 (Miss on (This device this device.) global winner.) Search2 Search4 (Miss on (Miss on this device ...
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... Figure 13-36. Timing Diagram for Devices Below the Winning Device in Block Number 1 Document #: 38-02042 Rev. *E cycle cycle cycle cycle cycle cycle cycle Search3 Search1 Search2 Search4 CYNSE70032 cycle cycle cycle Search1 Search3 (Miss on (Miss on this device.) this device.) Search2 Search4 (Miss on (Miss on this device.) this device.) Page 60 of 126 ...
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... Figure 13-37. Timing Diagram for Devices Above the Winning Device in Block Number 2 Document #: 38-02042 Rev. *E cycle cycle cycle cycle cycle cycle cycle Search3 Search1 Search2 Search4 CYNSE70032 cycle cycle cycle Search1 Search3 (Miss on (Miss on this device.) this device.) Search4 Search2 (Miss on (Miss on this device.) this device.) Page 61 of 126 ...
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... Figure 13-38. Timing Diagram for Globally Winning Device in Block Number 2 Document #: 38-02042 Rev. *E cycle cycle cycle cycle cycle cycle cycle Search3 Search1 Search2 Search4 CYNSE70032 cycle cycle cycle Search1 Search3 (Miss on (Hit but not this device.) winner.) Search2 Search4 (Global winner.) (Miss on this device ...
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... Figure 13-39. Timing Diagram for Devices Below the Winning Device in Block Number 2 Document #: 38-02042 Rev. *E cycle cycle cycle cycle cycle cycle cycle Search3 Search1 Search2 Search4 CYNSE70032 cycle cycle cycle Search1 Search3 (Miss on (Miss on this device.) this device.) Search2 Search4 (Miss on (Miss on this device.) this device.) Page 63 of 126 ...
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... Figure 13-40. Timing Diagram for Devices Above the Winning Device in Block Number 3 Document #: 38-02042 Rev. *E cycle cycle cycle cycle cycle cycle cycle Search1 Search3 Search2 Search4 CYNSE70032 cycle cycle cycle Search1 Search3 (Miss on (Miss on this device.) this device.) Search2 Search4 (Miss on (Miss on this device.) this device.) Page 64 of 126 ...
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... Figure 13-41. Timing Diagram for Globally Winning Device in Block Number 3 Document #: 38-02042 Rev. *E cycle cycle cycle cycle cycle cycle cycle Search3 Search1 Search2 Search4 CYNSE70032 cycle cycle cycle Search1 Search3 (Global (Miss on winner.) this device.) Search2 Search4 (Miss on (Hit but not this device ...
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... Document #: 38-02042 Rev. *E cycle cycle cycle cycle cycle cycle Search2 Search1 Search2 Search4 Except Device Number 30 (the Last Device) CYNSE70032 cycle cycle cycle cycle Search1 Search3 (Miss on (Miss on this device.) this device.) Search2 Search4 (Miss on (Miss on this device.) this device.) Page 66 of 126 ...
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... B. CMD[8:6] signals must be driven with the index of the SSR that will be used for storing the address of the matching Document #: 38-02042 Rev. *E cycle cycle cycle cycle cycle cycle Search1 Search3 Search2 Search4 (Device Number 30 in Depth-Cascaded Table) CYNSE70032 cycle cycle cycle cycle Search1 Search3 (Hit on some (Hit on some device above.) device above.) Search4 Search2 (Global miss; ...
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... CFG = 01010101 (136-bit configuration) Figure 13-44. x136 Table with 31 Devices Max Table Size 8K × 136 bits 64K × 136 bits 248K × 136 bits Number of CLK Cycles CYNSE70032 Note . During 136-bit Note 0 Odd B 0 (First matching entry) Latency in CLK Cycles ...
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... Search on Tables Configured as ×272 using a Single CYNSE70032 Device Figure 13-45 shows the timing diagram for a Search command in the 272-bit-configured table (CFG = 10101010) consisting of a single device for one set of parameters: TLSZ = 00, HLAT = 001, LRAM = 1, and LDEV = 1. The hardware diagram for this search subsystem is shown in Figure 13-46 ...
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... The matching address is always going to be location Note CFG = 10101010 (272-bit configuration) Figure 13-47. x272 Table with One Device Max Table Size 4K × 272 bits 32K × 272 bits 124K × 272 bits Number of CLK Cycles CYNSE70032 (First matching entry) Latency in CLK Cycles Page 70 of 126 ...
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... Search on Tables Configured as ×272 and Using up to Eight CYNSE70032 Devices The hardware diagram of the Search subsystem of eight devices is shown in Figure 13-48. The following are the parameters programmed into the eight devices. • First seven devices (devices 0–6): CFG = 10101010, TLSZ = 01, HLAT = 000, LRAM = 0, and LDEV = 0. ...
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... BHI[2:0] BHI[2:0] BHI[2:0] BHI[2:0] Figure 13-48. Hardware Diagram for a Table with Eight Devices Document #: 38-02042 Rev CYNSE70032 #0 LHO[ CYNSE70032 #1 LHO[ CYNSE70032 #2 LHO[1] BHI[2: CYNSE70032 #3 LHO[ CYNSE70032 # LHI LHI CYNSE70032 #5 LHO[ LHI CYNSE70032 #6 LHO[ LHI LHI CYNSE70032 #7 CYNSE70032 LHI LHO[ LHI LHO[0] ...
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... Figure 13-49. Timing Diagram for 272-bit Search Device Number 0 Document #: 38-02042 Rev. *E cycle cycle cycle cycle cycle cycle cycle Search2 Search3 Search1 Search1 Search2 (This device is the global winner.) CYNSE70032 cycle cycle cycle Search3 (Miss on (Miss on this device.) this device.) Page 73 of 126 ...
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... Figure 13-50. Timing Diagram for 272-bit Search Device Number 1 Document #: 38-02042 Rev. *E cycle cycle cycle cycle cycle cycle cycle Search2 Search3 Search1 Search1 (Miss on this device.) CYNSE70032 cycle cycle cycle Search3 (Miss on this device.) Search2 (This device is global winner.) Page 74 of 126 ...
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... C selects a pair of GMRs in each of the eight devices that apply to DQ data in cycles C and D. Document #: 38-02042 Rev. *E cycle cycle cycle cycle cycle cycle Search2 Search3 Search1 CMD[ signals that the search is a x272 bit search. CMD[8:3] in this cycle is ignored. CYNSE70032 cycle cycle cycle cycle ...
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... The hardware diagram of the search subsystem of 31 devices is shown in Figure 13-53. Each of the four blocks in the diagram represents a block of eight CYNSE70032 devices, except the last which has seven devices. The diagram for a block of eight devices is shown in Figure 13-54. The following are the parameters programmed into the 31 devices. ...
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... BHO[1] BHI[2] BHI[1] Block of 8 CYNSE70032s block 1 (devices 8–15) BHO[2] BHO[1] BHI[2] BHI[1] Block of 8 CYNSE70032s block 2 (devices 16–23) BHO[2] BHO[1] BHI[2] BHI[1] Block of 7 CYNSE70032s block 3 (devices 24–30) BHO[2] BHO[1] CYNSE70032 2 3 Miss Hit Hit Hit Hit Miss BHI[0] GND ...
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... BHI[2:0] BHI[2:0] BHI[2:0] BHI[2:0] 3 Figure 13-54. Hardware Diagram for a Block Eight Devices Document #: 38-02042 Rev CYNSE70032 #0 LHO[ CYNSE70032 #1 LHO[ CYNSE70032 #2 LHO[ CYNSE70032 # CYNSE70032 #4 LHO[ LHI LHI CYNSE70032 #5 LHO[ LHI LHI CYNSE70032 #6 LHO[ LHI LHI CYNSE70032 #7 CYNSE70032 LHI LHO[ LHI LHO[ LHI ...
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... Figure 13-55. Timing Diagram for Each Device in Block Number 0 (Miss on Each Device) Document #: 38-02042 Rev. *E cycle cycle cycle cycle cycle cycle cycle Search2 Search3 Search1 CYNSE70032 cycle cycle cycle Search1 Search2 Search3 (Miss on (Miss on (Miss on this device.) this device.) this device.) Page 79 of 126 ...
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... Figure 13-56. Timing Diagram for Each Device Above the Winning Device in Block Number 1 Document #: 38-02042 Rev. *E cycle cycle cycle cycle cycle cycle cycle Search2 Search3 Search1 CYNSE70032 cycle cycle cycle Search1 Search2 Search3 (Miss on (Miss on (Miss on this device.) this device.) this device.) Page 80 of 126 ...
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... Figure 13-57. Timing Diagram for Globally Winning Device in Block Number 1 Document #: 38-02042 Rev. *E cycle cycle cycle cycle cycle cycle cycle Search2 Search1 Search3 CYNSE70032 cycle cycle cycle Search1 Search2 Search3 (Miss on (Miss on (This device is this device.) this device.) g lobal winner.) Page 81 of 126 ...
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... Figure 13-58. Timing Diagram for Devices Below the Winning Device in Block Number 1 Document #: 38-02042 Rev. *E cycle cycle cycle cycle cycle cycle cycle Search2 Search3 Search1 CYNSE70032 cycle cycle cycle Search1 Search2 Search3 (Miss on (Miss on (Miss on this device.) this device.) this device.) Page 82 of 126 ...
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... Figure 13-59. Timing Diagram for Devices Above the Winning Device in Block Number 2 Document #: 38-02042 Rev. *E cycle cycle cycle cycle cycle cycle cycle Search2 Search3 Search1 CYNSE70032 cycle cycle cycle Search1 Search2 Search3 (Miss on (Miss on (Miss on this device.) this device.) this device.) hit in block 0 or block 1.) Page 83 of 126 ...
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... Note: Each bit in LHO[1:0] is the same logical signal. Figure 13-60. Timing Diagram for Globally Winning Device in Block Number 2 Document #: 38-02042 Rev. *E cycle cycle cycle cycle cycle cycle cycle Search2 Search3 Search1 CYNSE70032 cycle cycle cycle Search1 Search2 Search3 (Miss on (Global (Hit but this device ...
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... Figure 13-61. Timing Diagram for Devices Below the Winning Device in Block Number 2 Document #: 38-02042 Rev. *E cycle cycle cycle cycle cycle cycle cycle Search2 Search3 Search1 CYNSE70032 cycle cycle cycle Search1 Search2 Search3 (Miss on (Miss on (Miss on this device.) this device.) this device.) Page 85 of 126 ...
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... Figure 13-62. Timing Diagram for Devices Above the Winning Device in Block Number 3 Document #: 38-02042 Rev. *E cycle cycle cycle cycle cycle cycle cycle Search2 Search3 Search1 CYNSE70032 cycle cycle cycle Search1 Search2 Search3 (Miss on (Miss on (Miss on this device.) this device.) this device.) Page 86 of 126 ...
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... Note: Each bit in LHO[1:0] is the same logical signal. Figure 13-63. Timing Diagram for Globally WInning Device in Block Number 3 Document #: 38-02042 Rev. *E cycle cycle cycle cycle cycle cycle cycle Search2 Search3 Search1 CYNSE70032 cycle cycle cycle Search1 Search2 Search3 (Global (Hit but not (Miss on winner.) global winner.) this device.) ...
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... Figure 13-64. Timing Diagram for Devices Below the Winning Device in Block Number 3 Except Device Number 30 (the Last Device) Document #: 38-02042 Rev. *E cycle cycle cycle cycle cycle cycle cycle Search2 Search3 Search1 CYNSE70032 cycle cycle cycle Search1 Search2 Search3 (Miss on (Miss on (Miss on this device.) this device.) this device.) Page 88 of 126 ...
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... SADR[21:19 has a hit. DQ[67:0] must be driven with the 68-bit data ([135:68 compared to all locations 2 in the four 68-bits-word page. The CMD[2] signal must be driven to logic 0. Document #: 38-02042 Rev. *E cycle cycle cycle cycle cycle cycle cycle Search2 Search3 Search1 (Hit on some device above.) CYNSE70032 cycle cycle cycle Search1 ...
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... CFG = 10101010 (272-bit configuration) Figure 13-66. x272 Table with 31 Devices Max Table Size 4K × 272 bits 32K × 272 bits 124K × 272 bits Number of CLK Cycles CYNSE70032 . The matching address is always going Note Must be same in each of the 31 devices Latency in CLK Cycles 4 5 ...
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... DQ[67:66] will each of the two A and B cycles of the ×68-bit Search (Search1). DQ[67:66 each of the A and B cycles of the ×136-bit Search (Search2). DQ[67:66 each of the and D cycles of the ×272-bit Search (Search3). By having table designation bits, the CYNSE70032 device enables the creation of many tables of different widths in a bank of search engines. ...
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... The global FULL signal indicates to the table controller (the host ASIC) that all entries within a block are occupied and that no more entries can be learned. The CYNSE70032 device updates the signal to a data array after each Write or Learn command. Also using the NFA register as part of the SRAM address, the Learn command generates a Write cycle to the external SRAM (see Section 15.0, “ ...
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... PHS_L CMDV CMD[1:0] CMD[8: SADR[21:0] CE_L 1 1 WE_L 0 OE_L 0 SSV 0 SSF TLSZ = 00, LRAM = 1, LDEV = 1. Document #: 38-02042 Rev. *E cycle cycle cycle cycle cycle cycle Learn2 Learn1 X Comp2 Comp1 Figure 13-69. Learn Timing Diagram (TLSZ = 00) CYNSE70032 cycle cycle cycle cycle Page 93 of 126 ...
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... DQ z SADR[21:0] z CE_L z WE_L z OE_L z SSV z SSF TLSZ = 01, LRAM = 0, LDEV = 0. Figure 13-70. Learn Timing Diagram (TLSZ = 01 [Except on the Last Device]) Document #: 38-02042 Rev. *E cycle cycle cycle cycle cycle cycle cycle Learn2 Learn1 X Comp2 Comp1 CYNSE70032 cycle cycle cycle Page 94 of 126 ...
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... Learn is being performed on a 68-bit-configured table, and the Learn is being performed on a 136-bit-configured table. • Cycle 2: The host ASIC drives CMDV to 0. Document #: 38-02042 Rev. *E cycle cycle cycle cycle cycle cycle cycle Learn2 X Learn1 X Comp2 Comp1 Latency in CLK Cycles CYNSE70032 cycle cycle cycle Page 95 of 126 ...
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... CMDV CMD[8:0] BHI[2:0] BHI[2:0] BHI[2:0] BHI[2:0] BHI[2:0] Figure 14-1. Depth-Cascading to Form a Single Block Document #: 38-02042 Rev CYNSE70032 #0 LHO[ CYNSE70032 #1 LHO[ CYNSE70032 #2 LHO[1] BHI[2: CYNSE70032 #3 LHO[ CYNSE70032 # LHI CYNSE70032 #5 LHI LHO[ LHI CYNSE70032 #6 LHO[ LHI CYNSE70032 #7 LHI CYNSE70032 LHI LHO[ LHI LHO[0] 4 ...
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... Depth-Cascading Devices (Four Blocks) Figure 14-2 shows how to cascade up to four blocks. Each block except the last contains up to eight CYNSE70032 devices. The interconnection within each has been shown in the previous subsection with the cascading eight devices in a block. The interconnection between blocks for depth-cascading is important. For each Search, a block asserts BHO[2], BHO[1], and BHO[0] ...
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... Section 7.0, “Registers” on page 13 of this specification, describes the NFA and SSR registers. ADR[13:0] contains the address supplied on the DQ bus during PIO access to the CYNSE70032. Command bits 8, and 7 {CMD[8:6]} are passed from the command to the SRAM address bus. See Section 12.0, “Commands” on page 18, for more information. ID[4:0] is the ID of the device driving the SRAM bus (see Section 21.0, “ ...
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... At the end of cycle 6, the selected device floats ACK in a three-state condition, and a new command can begin. Document #: 38-02042 Rev [18:14 ID[4: ID[4: ID[4: ID[4: ID[4:0] . SRAM Write is a pipelined operation—new Note CYNSE70032 [13:0] Index[13:0] NFA[13:0] ADR13:0] ADR[13:0] SSR[13:0] Page 99 of 126 ...
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... The following explains the SRAM Read operation completed through a table eight devices using the following parameter: TLSZ = 01. Figure 15-2 diagrams a block of eight devices. The following assumes that SRAM access is successfully achieved through CYNSE70032 device number 0. Figure 15-3 and Figure 15-4 show timing diagrams for device number 0 and device number 7, respectively. ...
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... CMD[8:0] BHI[2:0] BHI[2:0] BHI[2:0] BHI[2:0] BHI[2:0] Document #: 38-02042 Rev CYNSE70032 #0 LHO[ CYNSE70032 #1 LHO[ CYNSE70032 #2 LHO[1] BHI[2: CYNSE70032 #3 LHO[ CYNSE70032 # LHI LHI CYNSE70032 #5 LHO[ LHI CYNSE70032 #6 LHO[ LHI LHI CYNSE70032 #7 Figure 15-2. Table of a Block of Eight Devices CYNSE70032 LHI LHO[ LHI LHO[0] ...
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... ALE_L z z SADR z SSV z z SSF TLSZ = 01, HLAT = 000, LRAM = 0, LDEV = 0. Figure 15-3. SRAM Read Through Device Number Block of Eight Devices Document #: 38-02042 Rev. *E cycle cycle cycle cycle Read Address CYNSE70032 cycle cycle cycle Address Driven by Selected CYNSE70032. Page 102 of 126 ...
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... TLSZ = 10. The diagram of this table is shown in Figure 15-5. The following assumes that SRAM access is being accom- plished through CYNSE70032 device number 0 and that device number 0 is the selected device. Figure 15-6 and Figure 15-7 show the timing diagrams for device number 0 and device number 30, respectively. ...
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... Block 1 (devices 8–15) CYNSE70032s BHO[2] BHO[1] BHI[2] BHI[1] Block of 8 Block 2 (devices 16–23) CYNSE70032s BHO[2] BHO[1] BHI[2] BHI[1] Block of 7 Block 3 (devices 24–30) CYNSE70032s BHO[2] BHO[1] CYNSE70032 BHI[0] GND SRAM BHO[0] BHI[0] GND BHO[0] GND BHI[0] BHO[0] BHI[0] BHO[0] Page 104 of 126 ...
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... TLSZ = 10, HLAT = 010, LRAM = 0, LDEV = 0. Figure 15-6. SRAM Read Through Device Number Bank of 31 Devices Document #: 38-02042 Rev. *E cycle cycle cycle cycle cycle cycle cycle Read Address Address (Device Number 0 Timing) CYNSE70032 cycle cycle cycle driven by the selected CYNSE70032 Page 105 of 126 ...
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... DQ[20:19] set to 10, to select the SRAM address. Writes into the SRAM are not supported. • Cycle 2: The host ASIC continues to drive DQ[67:0]. The data in this cycle is not used by the CYNSE70032. • Cycle 3: The host ASIC continues to drive DQ[67:0]. The data in this cycle is not used by the CYNSE70032. ...
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... Cycle 2: The host ASIC continues to drive DQ[67:0]. The data in this cycle is not used by the CYNSE70032. • Cycle 3: The host ASIC continues to drive DQ[67:0]. The data in this cycle is not used by the CYNSE70032. At the end of cycle 3, a new command can begin. The Write is a pipelined operation; however, the Write cycle appears at the SRAM bus with the same latency as the Search instruction (as measured from the second cycle of the Write command) ...
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... CMD[8:0] BHI[2:0] BHI[2:0] BHI[2:0] BHI[2:0] BHI[2:0] Document #: 38-02042 Rev CYNSE70032 #0 LHO[ CYNSE70032 #1 LHO[ CYNSE70032 #2 LHO[1] BHI[2: CYNSE70032 #3 LHO[ CYNSE70032 # LHI LHI CYNSE70032 #5 LHO[ LHI CYNSE70032 #6 LHO[ LHI LHI CYNSE70032 #7 Figure 15-9. Table of a Block of Eight Devices CYNSE70032 LHI LHO[ LHI LHO[0] ...
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... CE_L z ALE_L z SADR[21:0] z ACK z SSV z SSF TLSZ = 01, HLAT = XXX, LRAM = 0, LDEV = 0 Figure 15-10. SRAM Write Through Device Number Block of Eight Devices Document #: 38-02042 Rev. *E cycle cycle cycle cycle cycle Write Address CYNSE70032 cycle cycle cycle cycle cycle Address z Page 109 of 126 ...
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... Cycle 2: The host ASIC continues to drive DQ[67:0]. The data in this cycle is not used by the CYNSE70032. • Cycle 3: The host ASIC continues to drive DQ[67:0]. The data in this cycle is not used by the CYNSE70032. At the end of cycle 3, a new command can begin. The Write is a pipelined operation; however, the Write cycle appears at the SRAM bus with the same latency as the Search instruction (as measured from the second cycle of the Write command) ...
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... Block of 8 Block 2 (devices 16–23) CYNSE70032s BHO[2] BHO[1] BHI[2] BHI[1] Block of 7 Block 3 (devices 24–30) CYNSE70032s BHO[2] BHO[1] Figure 15-12. Table of 31 Devices (Four Blocks) CYNSE70032 BHI[0] GND SRAM BHO[0] BHI[0] GND BHO[0] GND BHI[0] BHO[0] BHI[0] BHO[0] Page 111 of 126 ...
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... SADR[21:0] ACK SSV SSF TLSZ = 01, HLAT = XXX, LRAM = 0, LDEV = 0. Figure 15-13. SRAM Write Through Device Number Bank of 31 Devices (Device 0 Timing) Document #: 38-02042 Rev. *E cycle cycle cycle cycle cycle Write Address CYNSE70032 cycle cycle cycle cycle cycle Address z Page 112 of 126 ...
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... PHS_L CMDV CMD[1:0] CMD[8: OE_L WE_L 1 CE_L 1 ALE_L 1 SADR[21:0] z ACK 0 SSV 0 SSF TLSZ = 01, HLAT = XXX, LRAM = 1, LDEV = 1. Figure 15-14. SRAM Write Through Device Number Bank of 31 CYNSE70032 Devices Document #: 38-02042 Rev. *E cycle cycle cycle cycle cycle cycle cycle Write Address x x (Device Number 30 Timing) ...
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... Application Figure 17-1 shows how a search engine subsystem can be formed using a host ASIC and Cypress’s CYNSE70032 bank. It also shows how this search engine subsystem is integrated in a switch or router. The CYNSE70032 can access synchronous as well as asynchronous SRAMs by allowing the host ASIC to set the same HLAT parameter in the all search engines within a bank of search engines ...
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... JTAG (1149.1) Testing The CYNSE70032 supports the Test Access Port (TAP) and Boundary Scan Architecture, as specified in the IEEE JTAG standard 1149.1. The pin interface to the chip consists of five signals with the standard definitions: TCK, TMS, TDI, TDO, and TRST_L. Table 18-1 describes the operations that the test access port controller supports, and Table 18-2 describes the TAP Device ID Register ...
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... LSB [0] 19.0 Electrical Specifications This section describes the electrical specifications, capacitance, operating conditions, DC characteristics, and AC timing param- eters for the CYNSE70032, as shown in Table 19-1 and Table 19-2. Operating Conditions for CYNSE70032 Table 19-1. DC Electrical Characteristics for CYNSE70032 Parameter Description I Input leakage current ...
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... AC Timing Waveforms Table 20-1 shows the AC timing parameters for the CYNSE70032 device; Table 20-2 shows the same parameters but for 2.5V. Figure 20-1 shows the device’s input wave form, and Figure 20-2 and Figure 20-3 show the device’s output load. Figure 20-4 shows a timing waveform diagram ...
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... V = 2.5V / +3.0V V DDQ AC Load 192 175 Figure 20-3. 2.5 I/O Output Load Equivalent for CYNSE70032 Notes: 14. Output loading is specified with pF Figure 20-3. Transition is measured at ± 200 mV from steady-state voltage. L 15. The load used for testing is shown in Figure 20- Document #: 38-02042 Rev 3.3V ...
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... Signal Group 4: SADR, CE_L, OE_L, WE_L, ALE_L, SSF, SSV. Signal Group 5: DQ, ACK, EOT. Document #: 38-02042 Rev. *E cycle cycle cycle cycle cycle tIHCH tIHCH tIHCH tICHCH tCKHOV tCKHOV tCKHSHZ tCKHSV tCKHSLZ Figure 20-4. AC Timing Waveforms with CLK2X CYNSE70032 cycle cycle cycle cycle cycle tCKHDZ tCKHDV Page 119 of 126 ...
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... Pinout Descriptions and Package Diagrams In the following figure and table the CYNSE70032 device pinout diagram and pinout descriptions are shown GND EOT NC NC VDD ACK FULL NC FULO1 3 DQ64 NC NC VDDQ VDD VDDQ 4 DQ62 NC VDD GND RSTL NC 5 DQ60 VDDQ NC DQ66 ...
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... I/O D14 I/O D15 3.3V/2.5V D16 I/O D17 I/O D18 I/O D19 D20 1. Output-T E3 Output-T E4 Input E17 E18 CYNSE70032 Signal Name Signal Type DQ63 I/O DQ59 I/O DQ55 I/O VDDQ 3.3V/2.5V NC DQ39 I/O DQ35 I/O NC DQ23 I/O DQ19 I/O NC DQ11 I/O ...
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... R1 3.3V/2.5V R2 Output-T R3 1.8V R4 Input R17 1.8V R18 Input R19 1.8V R20 Output-T T1 Output-T T2 Output-T T3 Output T4 CYNSE70032 Signal Name Signal Type BHO1 Output BHO2 Output FULI0 Input CLK2X Input SAD21 Output-T VDDQ 3.3V/2.5V VDD 1.8V FULI1 Input FULI2 Input VDDQ 3.3V/2.5V FULI3 ...
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... Y11 3.3V/2.5V Y12 I/O Y13 I/O Y14 3.3V/2.5V Y15 I/O Y16 I/O Y17 3.3V/2.5V Y18 I/O Y19 3.3V/2.5V Y20 1.8V J9 J10 CYNSE70032 Signal Name Signal Type CMD8 Input GND Ground VDDQ 3.3V/2.5V NC VDDQ 3.3V/2.5V DQ46 I/O DQ42 I/O NC DQ34 I/O DQ28 ...
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... GND K10 GND K11 GND K12 GND L9 GND 22.0 Ordering Information Table 22-1 provides ordering information. Table 22-1. Ordering Information Part Number CYNSE70032-66BGC CYNSE70032-66BGI CYNSE70032-83BGC Document #: 38-02042 Rev. *E Package Ball Signal Type Number Ground L10 Ground L11 Ground L12 Ground M9 Ground ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. Figure 23-1. Package CYNSE70032 51-85130-*A Page 125 of 126 ...
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... Document History Page Document Title: CYNSE70032 Network Search Engine Document Number: 38-02042 Issue REV. ECN NO. Date ** 111441 02/12/02 *A 116611 07/10/02 *B 118152 9/19/02 *C 121027 12/17/02 *D 123685 02/20/03 *E 126019 05/07/03 Document #: 38-02042 Rev. *E Orig. of Change Description of Change AFX New Data Sheet OOR Added industrial temp parts ...