LM8M64 Sharp Electronics, LM8M64 Datasheet - Page 19

• Manufacturer Part Number: LM8M64
• Manufacturer: Sharp Electronics

Specifications of LM8M64

• Lead Free Status / RoHS Status: Not Compliant

6. Module Driving Method
6-1. Circuit configuration
6-2. Display face configuration
6-3. Input data and control signal
Fig.12 shows the block diagram of the module's circuitry.
The display consists of 640×3(R,G,B)×240 dots as shown in Fig. 4.
The interface is single panel with double drive to be driven at 1/244duty ratio.
The LCD driver is 240 bits LSI, consisting of shift registers, latch circuits and LCD driver circuits. Input data
for each row 640×3 (R,G,B) will be sequentially transferred in the form of 8 bit parallel data through
shift registers from top left of the display together with clock signal (XCK).
When input of one row 640×3 (R,G,B) is completed, the data will be latched in the form of parallel
data corresponding to the signal electrodes by the falling edge of latch signal (LP) then, the corresponding
drive signals will be transmitted to the 640×3 lines of column electrodes of the LCD panel by the LCD
drive circuits.
At this time, scan start-up signal (YD) has been transferred from the scan signal driver to the 1st row of scan
electrodes, and the contents of the data signals are displayed on the 1st row of the display face according to
the combinations of voltages applied to the scan and signal electrodes of the LCD. While the data of 1st row
are being displayed, the data of 2nd row are entered. When data for 640×3 dots have been transferred, they
will be latched by the falling edge of LP, switching the display to the 2nd row.
Such data input will be repeated up to the 244th row of each display segment, from upper row to lower
rows, to complete one frame of display by time sharing method.
Then data input proceeds to the next display frame.
YD generates scan signal to drive horizontal electrodes.
Since DC voltage, if applied to LCD panel, causes chemical reaction in LC materials, causing deterioration of
the materials, drive wave-form shall be inverted at every display frame to prevent the generation of such DC
voltage.
Control signal M plays such a role.
Because of the characteristics of the CMOS driver LSI, the power consumption of the display module goes up
with the clock frequency of XCK.
To minimize data transfer speed of XCK clock the LSI has the system of transferring 8 bit parallel data
through the 8 lines of shift registers.
Thanks to this system the power consumption of the display module is minimized.
In this circuit configuration, 8 bit display data shall input to data input pins of D0-7 .
Furthermore, the display module has bus line system for data input to minimize the power consumption with
data input terminals of each driver LSI being activated only when relevant data input is fed.
Data input for column electrodes and chip select of driver LSI are made as follows:
SPEC No.
LC9
LC9
LC9
LC98109A
8109A
8109A
8109A
MODEL No.
LM
LM8M64
LM
LM
8M64
8M64
8M64
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