74HCT7030D-T NXP Semiconductors, 74HCT7030D-T Datasheet - Page 12
![](/photos/31/41/314108/sot136-1_sml.jpg)
74HCT7030D-T
Manufacturer Part Number
74HCT7030D-T
Description
Manufacturer
NXP Semiconductors
Datasheet
1.74HCT7030D-T.pdf
(22 pages)
Specifications of 74HCT7030D-T
Logic Family
HCT
Logical Function
FIFO Register
Number Of Elements
1
Number Of Bits
9
Number Of Inputs
9
Number Of Outputs
9
High Level Output Current
-6mA
Low Level Output Current
6mA
Package Type
SO
Propagation Delay Time
117ns
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
4.5V
Polarity
Non-Inverting
Technology
CMOS
Frequency (max)
36(Typ)MHz
Mounting
Surface Mount
Pin Count
28
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Quiescent Current
50uA
Output Type
3-State
Lead Free Status / RoHS Status
Compliant
Philips Semiconductors
AC WAVEFORMS
Shifting in sequence FIFO empty to FIFO full
With FIFO full; SI held HIGH in anticipation of empty location
December 1990
9-bit x 64-word FIFO register; 3-state
(1) HC : V
Fig.6
(1) HC : V
Fig.7
HCT: V
HCT: V
Waveforms showing the SI input to DIR output propagation
delay. The SI pulse width and SI maximum pulse frequency.
Waveforms showing bubble-up delay, SO input to DIR output
and DIR output pulse width.
M
M
M
M
= 50%; V
= 50%; V
= 1.3 V; V
= 1.3 V; V
I
I
I
I
= GND to V
= GND to V
= GND to 3 V.
= GND to 3 V.
CC
CC
.
.
12
Notes to Fig.6
1. DIR initially HIGH; FIFO is
2. SI set HIGH; data loaded into
3. DIR drops LOW, input stage
4. SI set LOW; data from first
5. DIR goes HIGH, status flag
6. Repeat process to load 2nd word
7. DIR remains LOW; with attempt
Notes to Fig.7
1. FIFO is initially full, shift-in is held
2. SO pulse; data in the output
3. DIR HIGH; when empty location
4. DIR returns to LOW; FIFO is full
5. SI brought LOW; necessary to
prepared for valid data.
input stage.
“busy”.
location “ripple through”.
indicates FIFO prepared for
additional data.
through to 64th word into FIFO.
to shift into full FIFO, no data
transfer occurs.
HIGH.
stage is unloaded, “bubble-up
process of empty locations
begins”.
reached input stage, flag
indicates FIFO is prepared for
data input.
again.
complete shift-in process, DIR
remains LOW, because FIFO is
full.
74HC/HCT7030
Product specification