PI74SSTU32864NB Pericom Semiconductor, PI74SSTU32864NB Datasheet - Page 6

• Manufacturer Part Number: PI74SSTU32864NB
• Manufacturer: Pericom Semiconductor

Specifications of PI74SSTU32864NB

• Logic Family: SSTU
• Logical Function: Registered Buffer
• Number Of Elements: 1
• Number Of Bits: 25
• Number Of Inputs: 25
• Number Of Outputs: 25
• High Level Output Current: -8mA
• Low Level Output Current: 8mA
• Package Type: LFBGA
• Propagation Delay Time: 3ns
• Operating Supply Voltage (typ): 1.8V
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Clock-edge Trigger Type: Posit/Negat-Edge
• Polarity: Non-Inverting
• Technology: CMOS
• Frequency (max): 270(Min)MHz
• Mounting: Surface Mount
• Pin Count: 96
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Not Compliant

Electrical Characteristics
Notes:
1.
Timing Requirements
Notes
1.
2.
3.
Parameters
Parameter
t
This parameter is not necessarily production tested.
Data and V
Data and clock inputs must be held at valid levels (not floating) a minimum time of t
I
V
The vendor must supply this value for full device description.
inact
V
f
t
I
DDD
act
clock
C
DD
t
t
I
OH
th
OL
W
su
I
I
(1)
(1)
REF
All inputs
Static Stand-by
Static Operating
Dynamic Operating
Clock only
Dynamic Operating - per
each data input, 1:1 mode
Dynamic Operating - per
each data input, 1:2 mode
Data inputsp
CK and CK
RST
inputs must be a low minimum time of t
Clock frequency
Pulse Duration, CK, CK, High or low
Differential inputs active time
Differential inputs inactive time
Description
Setup time
Hold Time
Over Recommended Operating Free Air Temperature range (See Figure 1)
Over Recommended Operating Free Air Temperature range
I
I
V
RST = GND
RST = V
RST = V
V
duty cycle
RST = V
V
duty cycle. One data input switch-
ing at half clock frequency, 50%
duty cycle
RST = V
V
duty cycle. One data input switch-
ing at half clock frequency, 50%
duty cycle
V
V
V
DCS before CK↑, CK↓, CSR high
DCS before CK↑, CK↓, CSR low
CSR DODT, CKE anddata before CK↑, CK↓
DCS, CSR DODT, CKE adn data before CK↑, CK↓
OH
OL
I
IL(AC)
IL(AC)
IL(AC)
I
ICR
I
= V
= V
= V
= 6 mA
= -6 mA
(1)
= 0.9V, V
DD
REF
DD
(2)
Description
CK and CK switching 50%
CK and CK switching 50%
CK and CK switching 50%
DD,
DD
DD
DD
or GND
or GND
act
±250mV
, V
, V
, V
V
max, after RST is taken high.
I =
I
I
I
ID
Test Conditions
= V
= V
= V
V
= 600mV
IH(AC)
IH(AC),
IH(AC),
IH(AC),
6
or V
or
or
or
IL(AC)
inact
I
O
max after RST is taken low.
= 0
1.7V
1.7V
1.9V
1.8V
V
DD
Min.
Min.
1.2
2.5
0.5
0.5
0.5
2
0.7
25-Bit 1:1 or 14-Bit 1:2
1
Configurable Buffer
Nom.
2.5
28
18
36
PI74SSTU32864
Max
270
10
15
PS8636B
Max.
100
0.5
3.5
±5
40
3
Units
MHz
Units
clock
clock
MHz
MHz
input
ns
µA/
µA/
data
mA
µA
07/26/04
pF
V