SSTUH32864EC/G NXP Semiconductors, SSTUH32864EC/G Datasheet - Page 2

• Manufacturer Part Number: SSTUH32864EC/G
• Manufacturer: NXP Semiconductors

Specifications of SSTUH32864EC/G

• Logic Family: SSTU
• Logical Function: Registered Buffer
• Number Of Elements: 1
• Number Of Bits: 25
• Number Of Inputs: 25
• Number Of Outputs: 25
• High Level Output Current: -12mA
• Low Level Output Current: 12mA
• Propagation Delay Time: 3ns
• Operating Supply Voltage (typ): 1.8V
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Clock-edge Trigger Type: Posit/Negat-Edge
• Polarity: Non-Inverting
• Technology: CMOS
• Frequency (max): 450(Min)MHz
• Mounting: Surface Mount
• Pin Count: 96
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

Philips Semiconductors
2. Features
3. Ordering information
Table 1:
T
9397 750 14137
Product data sheet
Type number
SSTUH32864EC/G Pb-free (SnAgCu
SSTUH32864EC
amb
= 0 C to +70 C.
Ordering information
Solder process
solder ball compound)
SnPb solder ball
compound
The SSTUH32864 is identical to SSTU32864 in function and performance, with
higher-drive outputs optimized to drive heavy load nets (such as stacked DRAMs) while
maintaining speed and signal integrity.
Configurable register supporting DDR2 Registered DIMM applications
Higher output drive strength version of SSTU32864 optimized for high-capacitive load
nets
Configurable to 25-bit 1 : 1 mode or 14-bit 1 : 2 mode
Controlled output impedance drivers enable optimal signal integrity and speed
Exceeds JESD82-7 speed performance (1.8 ns max. single-bit switching propagation
delay; 2.0 ns max. mass-switching)
Supports up to 450 MHz clock frequency of operation
Optimized pinout for high-density DDR2 module design
Chip-selects minimize power consumption by gating data outputs from changing state
Supports SSTL_18 data inputs
Differential clock (CK and CK) inputs
Supports LVCMOS switching levels on the control and RESET inputs
Single 1.8 V supply operation
Available in 96-ball, 13.5
Package
Name
LFBGA96
LFBGA96
Rev. 01 — 22 April 2005
5.5 mm, 0.8 mm ball pitch LFBGA package
Description
plastic low profile fine-pitch ball grid array package;
96 balls; body 13.5
plastic low profile fine-pitch ball grid array package;
96 balls; body 13.5
1.8 V high output drive DDR registered buffer
5.5
5.5
1.05 mm
1.05 mm
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
SSTUH32864
Version
SOT536-1
SOT536-1
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