STW81103ATR STMicroelectronics, STW81103ATR Datasheet
STW81103ATR
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STW81103ATR Summary of contents
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... MHz-762.5 MHz, the 1087.5 MHz-1525 MHz, the 2175 MHz-3050 MHz and the 4350 MHz-5000 MHz bands. The STW81103 is designed with STMicroelectronics advanced 0.35 µm SiGe process. Rev 3 STW81103 1/53 www.st.com ...
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Contents Contents 1 Block diagram and pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 Block diagram . ...
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STW81103 6.1.1 6.1.2 6.1.3 6.1.4 6.1.5 6.1.6 6.1.7 6.2 Timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of tables List of tables Table 1. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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STW81103 List of figures Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Block diagram and pin configuration 1 Block diagram and pin configuration 1.1 Block diagram Figure 1. Block diagram 6/53 STW81103 ...
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STW81103 1.2 Pin configuration Figure 2. Pin connection (top view) VDD_VCOA VDD_DIV2 VDD_OUTBUF OUTBUFP OUTBUFN VDD_DIV4 VDD_VCOB Table 1. Pin description Pin No Name 1 VDD_VCOA 2 VDD_DIV2 3 VDD_OUTBUF 4 OUTBUFP 5 OUTBUFN 6 VDD_DIV4 7 VDD_VCOB 8 VDD_ESD ...
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Block diagram and pin configuration Table 1. Pin description (continued) Pin No Name 10 ICP 11 REXT 12 VDD_CP 13 TEST1 14 LOCK_DET 15 TEST2 16 REF_CLK 17 VDD_PLL 18 EXTVCO_INN 19 EXTVCO_INP 20 VDD_BUFVCO 21 DBUS_SEL 22 VDD_DBUS 23 ...
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STW81103 2 Electrical specifications 2.1 Absolute maximum ratings Table 2. Absolute maximum ratings Symbol AV Analog supply voltage CC DV Digital supply voltage CC T Storage temperature stg Electrical static discharge (1) - HBM ESD - CDM-JEDEC standard - MM ...
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Electrical specifications 2.3 Digital logic levels Table 4. Digital logic levels Symbol Parameter V Low-level input voltage il V High-level input voltage ih V Schmitt trigger hysteresis hyst V Low-level output voltage ol V High-level output voltage oh 2.4 Electrical ...
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STW81103 Table 5. Electrical specifications (continued) Symbol Parameter Charge pump (3) I ICP sink/source CP Output voltage compliance V OCP range (4) Spurious VCOs (5) K VCOA sensitivity VCOA (5) K VCOB sensitivity VCOB Maximum temperature ΔT variation for continuous ...
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Electrical specifications Table 5. Electrical specifications (continued) Symbol Parameter External VCO Frequency range Input level Current consumption PLL miscellaneous I Current consumption PLL (5) (7) t Lockup time lock 1. In order to achieve best phase noise performance 1 V ...
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STW81103 2.5 Phase noise specification Table 6. Phase noise specification Parameter In-band phase noise floor – closed loop Normalized inband phase noise floor Inband phase noise floor direct output Inband phase noise floor divider by 2 Inband phase noise floor ...
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Electrical specifications Table 6. Phase noise specification Parameter VCO A with divider by 2 (1250 MHz-1525 MHz) – open loop Phase noise @ 1 kHz Phase noise @ 10 kHz Phase noise @ 100 kHz Phase noise @ 1 MHz ...
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STW81103 3 Typical performance characteristics Phase noise is measured with the Agilent E5052A Signal Source Analyzer. All closed-loop measurements are done with F properly set. The loop filter configuration is depicted in diagram , and the reference clock signal is ...
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Typical performance characteristics Figure 7. VCO A (div output) closed loop phase noise at 1.3876 GHz (F =200 kHz; F STEP I =1.5 mA) CP 0.4° rms Figure 9. VCO A (div output) closed loop phase ...
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STW81103 Figure 11. PFD frequency spurs (direct output; F =200 kHz) PFD -76 dBc @200KHz Figure 13. PFD frequency spurs (div output; F =800 kHz) PFD < -90 dBc @800KHz Typical performance characteristics Figure 12. PFD frequency spurs ...
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General description 4 General description Figure 1: Block diagram PLL frequency synthesizer. The STW81103 consists of two internal low-noise VCOs with buffer blocks, a divider divider low-noise PFD (phase frequency detector), a precise charge ...
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STW81103 5 Circuit description 5.1 Reference input stage The reference input stage is shown in F input, while the inverter used as the frequency reference buffer is AC coupled. ref Figure 15. Reference frequency input buffer F ref 5.2 Reference ...
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Circuit description 5.4 A and B counters The 5-bit A-counter and 12-bit B-counter, in conjunction with the selected dual modulus (16/17 or 19/20) prescaler, allow the generation of output frequencies that are spaced only by the reference frequency divided by ...
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STW81103 5.5 Phase frequency detector (PFD) The PFD takes inputs from the reference and the VCO dividers and produces an output proportional to the phase error. The PFD includes a delay gate that controls the width of the anti-backlash pulse. ...
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Circuit description Table 7. Current value vs. selection CPSEL2 Note: The current is output on pin ICP. During VCO auto-calibration, the ICP and VCTRL pins are forced to VDD/2. Figure 18. Loop ...
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STW81103 5.8 Voltage controlled oscillators 5.8.1 VCO selection The STW81103 integrates two low-noise VCOs to cover a wide band from: ● 2500 MHz to 3050 MHz and from 4350 MHz to 5000 MHz (direct output) ● 1250 MHz to 1525 ...
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Circuit description The SERCAL bit should be set to “1” at each division ratio change. The VCO calibration procedure takes approximately 7 periods of the PFD frequency. The maximum allowed F higher F , follow the steps below: PFD 1. ...
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STW81103 Table 9. VCO B performances vs. amplitude setting (Freq = 4.7 GHz) PLL_A[1: 5.9 Output stage The differential output signal of the synthesizer can be selected by software among three different signal paths (direct, divider ...
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Circuit description 5.10 External VCO buffer Although the main benefits of the STW81103 are the two wideband and low-noise VCOs, the capability to use an external VCO is also provided. The external VCO buffer is able to manage a signal ...
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STW81103 bus interface 2 The I C bus interface is selected by hardware connection of pin #21 (DBUS_SEL Data is transmitted from microprocessor to the STW81103 through the 2-wire (SDA and 2 SCL) ...
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I C bus interface Figure 21. START and STOP conditions SCL SDA START 6.1.3 Byte format and acknowledge Every byte put on the SDA line must be 8 bits long, starting with the most significant bit (MSB), and be ...
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STW81103 6.1.5 Single-byte write mode Following a START condition, the master sends a device select code with the RW bit set to 0. The STW81103 sends an acknowledge and waits for the 1-byte internal sub-address that provides access to the ...
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I C bus interface 6.2 Timing specification Figure 23. Data and clock SDA SCL t Table 14. Data and clock timing specifications Symbol cwh t cwl Figure 24. Start and stop SDA SCL 30/53 ...
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STW81103 Table 15. Start and stop timing specifications Symbol t start t stop Figure 25. Ack SDA SCL Table 16. Ack timing specifications Symbol Parameter Clock to data start time Data to clock down stop time ...
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I C bus interface 2 6 registers The STW81103 has 6 write-only registers and 1 read-only register. 6.3.1 Write-only registers Table 17 gives a short description of the write-only registers. Table 17. Write-only registers HEX code 0x00 ...
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STW81103 B_COUNTER MSB b7 b6 B10 B9 B[10:3]. B counter value (bit B11 in the previous register, bits B[2:0] in the next register) A_COUNTER MSB Bits B[2:0] for B_COUNTER, A_COUNTER values. REF_DIVIDER MSB ...
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I C bus interface CALIBRATION MSB b7 b6 INITCAL SERCAL This register controls the VCO calibrator using the following values: INITCAL: for test purposes only, must be set to 0 SERCAL starts the VCO auto-calibration (automatically reset ...
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STW81103 6.4 VCO calibration procedure Calibration of the VCO center frequency is activated when the SERCAL bit (CALIBRATION register bit[6]) is set program the device properly while ensuring VCO calibration, perform the following steps before every channel ...
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SPI digital interface 7 SPI digital interface 7.1 General features The SPI digital interface is selected by hardware connection of pin #21 (DBUS_SEL) to 3.3 V. The STW81103 IC is programmed by means of a high-speed serial-to-parallel interface with write ...
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STW81103 Table 19. SPI data structure (MSB is sent first) MSB Address A1 A0 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 Table 20. ...
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SPI digital interface 7.3 Bit tables Table 22. Bits at 00h and ST1 Serial interface address = 00h Bit [23] [22] [21] [20] [19] [18] [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] PSC_SEL [7] [6] [5] SELEXTCAL ...
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STW81103 Table 23. Bits at 01h and ST2 Serial interface address = 01h Bit [23] OUTBUF_CTRL_EN [22] CAL_AUTOSTART_EN [21] [20] [19] [18] [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] ...
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SPI digital interface The LO output frequency is programmed by setting the proper value for A, B and R according to the following formula: × OUT R D where R equals and P is the ...
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STW81103 8 Application information The STW81103 features three different alternately selectable bands: direct output (2.5 to 3.05 GHz and 4.35 to 5.0 GHz), divided by 2 (1.25 to 1.525 GHz and 2.175 to 2.5 GHz) and divided by 4 (625 ...
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Application information Alternatively, you can combine the two outputs in other ways. A first topology for the direct output (2.5 to 5.0 GHz) is suggested in and a matching network to adapt the output to a 50Ω load. The two ...
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STW81103 Figure 30. Evaluation board (EVB4G) matching network (MATCH_EVB4G.dsn) Vcc 50 ohm RF OUTP RF OUTN 50 ohm Vcc For differential to single conversion, the 50 to 100Ω Johanson balun is recommended (3700BL15B100). 8.2 Divided by 2 output If your ...
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Application information A first solution to combine the differential outputs is the lumped LC type balun tuned in the 2 GHz band ( Figure 32 Figure 32. LC lumped balun for divided by 2 output (MATCH_LC_LUMP_2G.dsn) 50 ohm RF OUTP ...
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STW81103 For differential to single conversion, the 50 to 100Ω Johanson balun (1600BL15B100) is recommended. 8.3 Divided by 4 output The topology, components, values and considerations output (MATCH_LC_LUMP_1G_DIFF.dsn). As for the previous sections, a solution to combine ...
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Application information Figure 35. Evaluation board (EVB1G) matching network (MATCH_EVB1G.dsn) 25 ohm RF OUTP RF OUTN 25 ohm 8.4 Evaluation kit An evaluation kit can be delivered upon request, including the following: ● Evaluation board ● GUI (graphical user interface) ...
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STW81103 9 Application diagram Figure 36. Typical application diagram VDD 1 1n 22p 10 VDD 1 RF Out VDD 1 VDD 1 1n 22p 10 loop filter Note: 1 See Section 8: Application information 2 EXT_PD, ADD2, ADD1 (and ADD0 ...
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Application diagram Figure 37. Ping-pong architecture diagram Note: 1 See Section 8: Application information 2 EXT_PD, ADD2, ADD1 (and ADD0 when the I on the board. 3 Loop filter values are for F 4 For best performance VDD (20 μ ...
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STW81103 Figure 38. Application diagram with external VCO (LO output from STW81103) Note: See Section 8: Application information Figure 39. Application diagram with external VCO (LO output from VCO) for further information on output matching topology. Application diagram 49/53 ...
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Package mechanical data 10 Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK packages, which have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on ...
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STW81103 Table 25. Package dimensions Ref ddd Min. Typ. 0.800 0.900 0.020 0.650 0.200 0.180 0.250 4.850 5.000 4.750 2.950 3.100 4.850 5.000 4.750 2.950 ...
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... Ordering information 11 Ordering information Table 26. Order codes Part number STW81103AT STW81103ATR 12 Revision history Table 27. Document revision history Date 18-Jul-2007 14-Aug-2007 28-Mar-2008 52/53 Temp range, ° VFQFPN28 - VFQFPN28 Revision 1 Initial release. Chapter 8: Application information Added 2 VCO calibration procedure Table 1: Pin description Updated ...
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... STW81103 Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...