CYII4SD1300AA-QDC Cypress Semiconductor Corp, CYII4SD1300AA-QDC Datasheet - Page 29

• Manufacturer Part Number: CYII4SD1300AA-QDC
• Manufacturer: Cypress Semiconductor Corp
• Type: CMOSr

Specifications of CYII4SD1300AA-QDC

• Sensor Image Color Type: Color
• Sensor Image Size: 1280x1024Pixels
• Operating Supply Voltage (typ): 5V
• Package Type: LCC
• Mounting: Surface Mount
• Pin Count: 84
• Lead Free Status / RoHS Status: Not Compliant

Document Number: 38-05707 Rev. *C
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No.
clk_x
shy
dccon
dcref
gnd
vdd
sin
sync_y\l
clk_yl
eos_yl\
bitinvert
select
reset
d9
d8
d7
d6
d5
d4
d3
d2
d1
d0
gnd
vdd
gnd_ab
vdd_array
vdd_dig
gnd_dig
vdd_an
vdd_resetl
gnd_an
vhigh_adc
clk_adc
Name
D
D
A
A
A
A
D
D
D
D
D
D
D
W
W
W
W
W
W
W
W
W
W
A
A
A
A
D
D
A
A
A
A
D
Type
I
I
I
O
G
P
I
I
I
O
I
I
I
O
O
O
O
O
O
O
O
O
O
G
P
G
P
P
G
P
P
G
I
I
I/O
Shifts on falling edge
Column parallel track and hold
control voltage for DC reference gener-
ation
reference voltage
Column amplifier calibration signal
0 = start left shift register
clock left shift register
low 1st clk_yl pulse after last row
High active, 1 = invert bits
High active
High active
MSB
LSB
+ 5 V DC
Anti-blooming drain voltage
+ 5 V DC
+ 5 V DC
+ 5 V DC
5 V DC default
(5.5 V for large output swing)
4…4.5 V for double slope mode
+ 4 V DC
ADC Clock
Description
clock X shift register
1 = hold; 0 = track
Connect to GND (default)
Should be +/- 1.2 V, depends on dccon
1 = calibrate, see timing diagram
low active (0=sync)
Shifts on falling edge
Active low
inverts ADC output bits
selects row indicated by left/right shift register
resets row indicated by left/right shift register
ADC output
GND or +1V for improved anti-blooming
Pixel power supply
ADC digital power supply
ADC ground of digital circuits
ADC analog power supply
VDD for reset by left shift register
ADC ground of analog circuits
High ADC reference voltage
Converts on falling edge
CYII4SM1300AA
Signal
Page 29 of 35
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