XCM20014IBMN Freescale, XCM20014IBMN Datasheet - Page 41

• Manufacturer Part Number: XCM20014IBMN
• Manufacturer: Freescale
• Type: CMOSr

Specifications of XCM20014IBMN

• Sensor Image Color Type: Color
• Sensor Image Size Range: 250,920 to 480,000Pixels
• Sensor Image Size: 640x480Pixels
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 40C
• Package Type: CLCC
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / RoHS Status: Supplier Unconfirmed

MCM20014
6.0 I
The I
with the Motorola bus (called M-Bus) that is available on
many microprocessor products. The I
rial two-wire half-duplex interface that features bidirec-
tional operation, master or slave modes, and multi-
master environment support. The clock frequency on
the system is governed by the slowest device on the
board. The SDATA and SCLK are the bidirectional data
and clock pins, respectively. These pins are open drain
and will require a pull-up resistor to VDD of 1.5 kΩ to 10
kΩ (see
The I
into the Program Control Registers in the MCM20014.
The I
trol Register for verification or test considerations. The
MCM20014 is a slave only device that supports a max-
imum clock rate (SCLK) of 100 kHz while reading or
writing only one register address per I 2 C start/stop cy-
cle. The following sections will be limited to the methods
for writing and reading data into the MCM20014 regis-
ter.
For a complete reference to I
Theory to Practice” by Dominique Paret and Carll-
Fenger, published by John Wiley & Sons, ISBN
0471962686.
6.1 MCM20014 I 2 C Bus Protocol
The MCM20014 uses the I 2 C bus to write or read one
register byte per start/stop I 2 C cycle as shown in
25
Address
Number
and
vcw[7]
msb (7)
2
7 - 0
2
2
2
53
C Serial Interface
Bit
C is an industry standard which is also compatible
C bus can also read the data in the Program Con-
C is used to write the required user system data
Figure
h
page
26. These figures will be used to describe
48).
Virtual Col-
umn Width
Function
vcw[6]
6
Table 43. CFCM Virtual Frame Column Width LSB Register
2
C, see “The I
In conjunction with the CFCM Virtual Frame Column Width MSB
(Table
vcw[13:0]. WOI is always top-left justified in Virtual Frame.
vcw
vcw
Freescale Semiconductor, Inc.
vcw[5]
d
d
For More Information On This Product,
5
minimum = wcw
minimum = wcw
CFCM Virtual Frame Column Width LSB
42) Register, forms the 14-bit Virtual Frame Column Width
2
C contains a se-
2
C Bus from
Go to: www.freescale.com
vcw[4]
Figure
4
d
d
+ 11 (CFCM)
+ 14 (SFCM)
Description
the various parts of the I 2 C protocol communications as
it applies to the MCM20014.
MCM20014 I 2 C bus communication is basically com-
posed of following parts: START signal, MCM20014
slave address (0110011
W bit, an acknowledgment signal from the slave, 8 bit
data transfer followed by another acknowledgment sig-
nal, STOP signal, Repeated START signal, and clock
synchronization.
6.2 START Signal
When the bus is free, i.e. no master device is engaging
the bus (both SCLK and SDATA lines are at logical “1”),
a master may initiate communication by sending a
START signal. As shown in
is defined as a high-to-low transition of SDATA while
SCLK is high. This signal denotes the beginning of a
new data transfer and wakes up all the slaves on the
bus.
6.3 Slave Address Transmission
The first byte of a data transfer, immediately after the
START signal, is the slave address transmitted by the
master. This is a 7-bit calling address followed by a R/
W bit. The seven-bit address for the MCM20014, start-
ing with the MSB (AD7) is 0110011
calling address on the SDATA line may only be
changed while SCLK is low as shown in
data on the SDATA line is valid on the High to Low sig-
nal transition on the SCLK line. The R/W bit following
the 7-bit tells the slave the desired direction of data
transfer:
vcw[3]
3
vcw[2]
2
b
) transmission followed by a R/
Figure
vcw[1]
1
25, a START signal
b
. The transmitted
Figure
11101101
(750 col.)
Default
vcw[0]
Reset
State
lsb (0)
ED
25. The
MOTOROLA
h
b
41