XCM20014IBMN Freescale, XCM20014IBMN Datasheet - Page 30

• Manufacturer Part Number: XCM20014IBMN
• Manufacturer: Freescale
• Type: CMOSr

Specifications of XCM20014IBMN

• Sensor Image Color Type: Color
• Sensor Image Size Range: 250,920 to 480,000Pixels
• Sensor Image Size: 640x480Pixels
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 40C
• Package Type: CLCC
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / RoHS Status: Supplier Unconfirmed

MOTOROLA
30
5.5 Sensor Interface Block
5.5.1 Sensor Output Control
The sensor output control registers define how the win-
dow of interest is captured and what data is output from
the MCM20014.
The
how the data is captured and how the data is to be pro-
vided at the output.
The sms bit defines the shutter mode, CFCM or SFCM,
of the device as described in
default mode.
Setting the cms bit will stop the current CFCM output
data stream at the end of the current frame. Unsetting
this bit (cms = 0
stream. The MCM20014 is in CFCM in default. The user
may use this bit to capture data in the CFCM mode
while using the SYNC pin. The SYNC pin triggers a sin-
gle frame of data to be output from the device in the
CFCM mode. Please refer to
a timing diagram of this mode.
Address
msb (7)
Capture Mode Control Register; Table
2 - 0
cpe
32
6
5
4
3
h
b
) will resume the output of the frame
Enable
Enable
pander
pander
White
Slope
Black
Com-
Com-
Knee
FUO
fuo
6
section
Figure 19, on page 14
FUO
0
1
0
1
0
1
000
001
010
011
100
101
110
111
b
b
b
b
b
b
Freescale Semiconductor, Inc.
= Disable White Bad Pixel Replacement
= Enable White Bad Pixel Replacement
= Disable Black Bad Pixel Replacement
= Enable Black Bad Pixel Replacement
= Invalid when cpb[2:0]
= 1:1 input:output
b
wpe
b
b
b
b
b
b
b
For More Information On This Product,
= 127 on the output axis.
= 47 on the output axis.
= 95 on the output axis.
5
= linear
= 15 on the output axis.
= 31 on the output axis.
= 63 on the output axis.
= 79 on the output axis.
2.1.3. CFCM is the
Table 23. Post ADC Control Register
24, defines
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Post ADC Control
bpe
4
for
≠
000
The frc bit is used to enable or disable the Frame Rate
Clamp. Unsetting this bit will turn off the frame rate
clamp and the output dark level will begin to drift over
frames. The frame rate clamp is enabled in default
mode.
The sp bit is used to define whether SOF is active high
or low. SOF is active high in default.
The ve bit is used to determine whether VCLK is output
at the beginning of all the rows including virtual frame
rows or for the WOI rows only. The default is WOI only.
The vp bit is used to define whether VCLK is active high
or low. VCLK is active high in default.
The he bit is used to determine whether HCLK is output
continously or for the WOI pixels only. The default is
WOI only.
The hp bit is used to define whether HCLK is active high
or low. HCLK is active high in default.
cps
b
3
cpb[2]
2
cpb[1]
1
Default
cpb[0]
lsb (0)
000
30
0
1
1
0
b
b
b
b
h
b
MCM20014