AT94K05AL-25DQU Atmel, AT94K05AL-25DQU Datasheet - Page 97
AT94K05AL-25DQU
Manufacturer Part Number
AT94K05AL-25DQU
Description
Manufacturer
Atmel
Datasheet
1.AT94K05AL-25DQU.pdf
(204 pages)
Specifications of AT94K05AL-25DQU
Device System Gates
5000
Propagation Delay Time
12.1ns
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Operating Temperature Classification
Industrial
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Mounting
Surface Mount
Pin Count
208
Package Type
PQFP
Lead Free Status / RoHS Status
Compliant
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1138I–FPSLI–1/08
Figure 4-29. Effects of Unsynchronized OCR Latching in Up/Down Mode
Note:
Figure 4-30. Effects of Unsynchronized OCR Latching in Overflow Mode.
Note:
During the time between the write and the latch operation, a read from the Output Compare
Registers will read the contents of the temporary location. This means that the most recently
written value always will read out of OCR0 and OCR2.
When the Output Compare Register contains $00 or $FF, and the up/down PWM mode is
selected, the output PE1(OC0/PWM0)/PE3(OC2/PWM2) is updated to Low or High on the next
compare match according to the settings of COMn1/COMn0. This is shown in
overflow PWM mode, the output PE1(OC0/PWM0)/PE3(OC2/PWM2) is held Low or High only
when the Output Compare Register contains $FF.
Compare Value Changes
1. n = 0 or 2
1. n = 0 or 2
Compare Value Changes
Unsynchronized OCn
Synchronized OCn
Synchronized OCn
Unsynchronized OCn
(1)
(1)
(1)
Latch
Latch
Latch
(1)
Latch
AT94KAL Series FPSLIC
Compare Value Changes
Glitch
Compare Value Changes
Glitch
Counter Value
Compare Value
PWM Output OCn
Counter Value
Compare Value
PWM Output OCn
Counter Value
Compare Value
PWM Output OCn
Counter Value
Compare Value
PWM Output OCn
Table
4-16. In
(1)
(1)
(1)
(1)
97
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