AT94K05AL-25DQU Atmel, AT94K05AL-25DQU Datasheet - Page 104
AT94K05AL-25DQU
Manufacturer Part Number
AT94K05AL-25DQU
Description
Manufacturer
Atmel
Datasheet
1.AT94K05AL-25DQU.pdf
(204 pages)
Specifications of AT94K05AL-25DQU
Device System Gates
5000
Propagation Delay Time
12.1ns
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Operating Temperature Classification
Industrial
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Mounting
Surface Mount
Pin Count
208
Package Type
PQFP
Lead Free Status / RoHS Status
Compliant
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104
AT94KAL Series FPSLIC
Timer/Counter1 Control Register B – TCCR1B
• Bit 7 - ICNC1: Input Capture1 Noise Canceler (4 CKs)
When the ICNC1 bit is cleared (zero), the input capture trigger noise canceler function is dis-
abled. The input capture is triggered at the first rising/falling edge sampled on the PE7(ICP) –
input capture pin – as specified. When the ICNC1 bit is set (one), four successive samples are
measured on the PE7(ICP) – input capture pin, and all samples must be High/Low according to
the input capture trigger specification in the ICES1 bit. The actual sampling frequency is XTAL
clock frequency.
• Bit 6 - ICES1: Input Capture1 Edge Select
While the ICES1 bit is cleared (zero), the Timer/Counter1 contents are transferred to the Input
Capture Register – ICR1 – on the falling edge of the input capture pin – PE7(ICP). While the
ICES1 bit is set (one), the Timer/Counter1 contents are transferred to the Input Capture Register
– ICR1 – on the rising edge of the input capture pin – PE7(ICP).
• Bit 5 - ICPE: Input Captive Pin Enable
This bit must be set by the user to enable the Input Capture Function of timer1. Disabling pre-
vents unnecessary register copies during normal use of the PE7 port.
• Bit 4 - Res: Reserved Bit
This bit is reserved in the FPSLIC and will always read zero.
• Bit 3 - CTC1: Clear Timer/Counter1 on Compare Match
When the CTC1 control bit is set (one), the Timer/Counter1 is reset to $0000 in the clock cycle
after a compareA match. If the CTC1 control bit is cleared, Timer/Counter1 continues counting
and is unaffected by a compare match. When a prescaling of 1 is used, and the compareA reg-
ister is set to C, the timer will count as follows if CTC1 is set:
... | C-1 | C | 0 | 1 | ...
When the prescaler is set to divide by 8, the timer will count like this:
... | C-1, C-1, C-1, C-1, C-1, C-1, C-1, C-1 | C, C, C, C, C, C, C, C | 0, 0, 0, 0, 0, 0, 0, 0 | ...
In PWM mode, this bit has a different function. If the CTC1 bit is cleared in PWM mode, the
Timer/Counter1 acts as an up/down counter. If the CTC1 bit is set (one), the Timer/Counter
wraps when it reaches the TOP value. Refer to
• Bits 2,1,0 - CS12, CS11, CS10: Clock Select1, Bits 2, 1 and 0
The Clock Select1 bits 2,1 and 0 define the prescaling source of Timer/Counter1.
Bit
$2E ($4E)
Read/Write
Initial Value
7
ICNC1
R/W
0
6
ICES1
R/W
0
5
ICPE
0
R/W
4
-
R
0
page 107
3
CTC1
R/W
0
for a detailed description.
2
CS12
R/W
0
1
CS11
0
R/W
0
CS10
R/W
0
1138I–FPSLI–1/08
TCCR1B
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