AT94K05AL-25BQX Atmel, AT94K05AL-25BQX Datasheet - Page 63
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AT94K05AL-25BQX
Manufacturer Part Number
AT94K05AL-25BQX
Description
Manufacturer
Atmel
Datasheet
1.AT94K05AL-25BQX.pdf
(204 pages)
Specifications of AT94K05AL-25BQX
Device System Gates
5000
Propagation Delay Time
12.1ns
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Operating Temperature Classification
Commercial
Operating Temperature (min)
0C
Operating Temperature (max)
70C
Mounting
Surface Mount
Pin Count
144
Package Type
LQFP
Lead Free Status / RoHS Status
Compliant
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4.16.1
Figure 4-12. Reset Logic
1138I–FPSLI–1/08
AVR RESET
RESET/
SFTCR
BIT 0
Reset Sources
CONFIG
LOGIC
FPGA
POR
OSCILLATOR
WATCHDOG
The embedded AVR core has five sources of reset:
During reset, all I/O registers except the MCU Status register are then set to their Initial Values,
and the program starts execution from address $0000. The instruction placed in address $0000
must be a JMP – absolute jump instruction to the reset handling routine. If the program never
enables an interrupt source, the interrupt vectors are not used, and regular program code can be
placed at these locations. The circuit diagram in
defines the timing and electrical parameters of the reset circuitry.
INTERNAL
• External Reset. The MCU is reset immediately when a low-level is present on the RESET or
• Power-on Reset. The MCU is reset upon chip power-up and remains in reset until the FPGA
• Watchdog Reset. The MCU is reset when the Watchdog Timer period expires and the
• Software Reset. The MCU is reset when the SRST bit in the Software Control register is set
• JTAG AVR Reset. The MCU is reset as long as there is a logic one in the Reset Register, one
SYSTEM
CLOCK
TIMER
AVR RESET pin.
configuration has entered Idle mode.
watchdog is enabled.
(one).
of the scan chains of the JTAG system. See
76.
MCU STATUS
DATA BUS
DELAY COUNTERS
JTAG RESET
REGISTER
SEL [4:0] CONTROLLED
BY FPGA CONFIGURATION
“IEEE 1149.1 (JTAG) Boundary-scan” on page
AT94KAL Series FPSLIC
Figure 4-12
FULL
shows the reset logic.
S
R
Q
INTERNAL
RESET
Table 4-7
63
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