AT94K05AL-25BQX Atmel, AT94K05AL-25BQX Datasheet - Page 106

• Manufacturer Part Number: AT94K05AL-25BQX
• Manufacturer: Atmel

Specifications of AT94K05AL-25BQX

• Device System Gates: 5000
• Propagation Delay Time: 12.1ns
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temperature Classification: Commercial
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / RoHS Status: Compliant

106
AT94KAL Series FPSLIC
The Timer/Counter1 is realized as an up or up/down (in PWM mode) counter with read and write
access. If Timer/Counter1 is written to and a clock source is selected, the Timer/Counter1 con-
tinues counting in the timer clock-cycle after it is preset with the written value.
Timer/Counter1 Output Compare Register – OCR1AH AND OCR1AL
Timer/Counter1 Output Compare Register – OCR1BH AND OCR1BL
The output compare registers are 16-bit read/write registers.
The Timer/Counter1 Output Compare Registers contain the data to be continuously compared
with Timer/Counter1. Actions on compare matches are specified in the Timer/Counter1 Control
and Status register. A compare match does only occur if Timer/Counter1 counts to the OCR
value. A software write that sets TCNT1 and OCR1A or OCR1B to the same value does not gen-
erate a compare match.
A compare match will set the compare interrupt flag in the CPU clock cycle following the com-
pare event.
Since the Output Compare Registers – OCR1A and OCR1B – are 16-bit registers, a temporary
register TEMP is used when OCR1A/B are written to ensure that both bytes are updated simul-
taneously. When the CPU writes the high byte, OCR1AH or OCR1BH, the data is temporarily
stored in the TEMP register. When the CPU writes the low byte, OCR1AL or OCR1BL, the
TEMP register is simultaneously written to OCR1AH or OCR1BH. Consequently, the high byte
OCR1AH or OCR1BH must be written first for a full 16-bit register write operation.
The TEMP register is also used when accessing TCNT1, and ICR1. If the main program and
also interrupt routines perform access to registers using TEMP, interrupts must be disabled dur-
ing access from the main program and interrupt routines.
Bit
$2B ($4B)
$2A ($4A)
Read/Write
Initial Value
Bit
$29 ($49)
$28 ($48)
Read/Write
Initial Value
15
MSB
7
R/W
R/W
0
0
15
MSB
7
R/W
R/W
0
0
14
6
R/W
R/W
0
0
14
6
R/W
R/W
0
0
13
5
R/W
R/W
0
0
13
5
R/W
R/W
0
0
12
4
R/W
R/W
0
0
12
4
R/W
R/W
0
0
11
3
R/W
R/W
0
0
11
3
R/W
R/W
0
0
10
2
R/W
R/W
0
0
10
2
R/W
R/W
0
0
9
1
R/W
R/W
0
0
9
1
R/W
R/W
0
0
8
LSB
0
R/W
R/W
0
0
8
LSB
0
R/W
R/W
0
0
1138I–FPSLI–1/08
OCR1AH
OCR1AL
OCR1BH
OCR1BL