IP-POSPHY/P2 Altera, IP-POSPHY/P2 Datasheet - Page 33

• Manufacturer Part Number: IP-POSPHY/P2
• Manufacturer: Altera

Specifications of IP-POSPHY/P2

• Lead Free Status / RoHS Status: Not Compliant

Chapter 3: Functional Description
Internal Architecture
Figure 3–9. Sink MegaCore Function Block Diagram
Figure 3–10. Source MegaCore Function Block Diagram
© November 2009 Altera Corporation
Control
Control
Data
Data
Link-Layer or
Link-layer or
PHY-Layer
PHY-Layer
Interface
Interface
Multiplexer
Source
Sink
Each MegaCore function includes a separate receiver and transmitter, which can be
instantiated in a single device or separate devices.
There are many similarities in the internal architecture of these blocks. The main
difference is in the non-symmetrical handshaking on the physical interface between
receive and transmit directions.
Figure 3–9 on page 3–5
on page 3–5
POS-PHY Interface
Each POS-PHY supports single and multi-PHY implementations. The POS-PHY
interface interfaces to an internal multiplexer, which allows access to multiple/single
internal packet FIFO buffers. Status information from the FIFO buffers is used to
control the POS-PHY interface. The source interface provides polled or direct packet
available modes.
Port N
Port 2
Port 1
Port 0
Port N
Port 2
Port 1
Port 0
shows the source MegaCore function block diagram.
Packet Data
Packet Data
Conversion
Conversion
(narrower)
(wider)
Width
Width
shows the sink MegaCore function block diagram.
1
1
Preliminary
Packet
Packet
FIFO
FIFO
2
2
'B' Interface Options
'B' Interface Options
Packet Data
Packet Data
Conversion
Conversion
(narrower)
(wider)
Width
Width
POS-PHY Level 2 and 3 Compiler User Guide
3
3
Link-layer or
Link-layer or
PHY-Layer
PHY-Layer
Interface
Interface
Source
Sink
Control
Control
Data
Data
Figure 3–10
4
4
3–5