CY7C374I-83JC Cypress Semiconductor Corp, CY7C374I-83JC Datasheet - Page 7

• Manufacturer Part Number: CY7C374I-83JC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C374I-83JC

• Family Name: FLASH370i
• # Macrocells: 128
• Number Of Usable Gates: 3200
• Propagation Delay Time: 15ns
• Number Of Logic Blocks/elements: 8
• # I/os (max): 64
• Operating Supply Voltage (typ): 5V
• In System Programmable: Yes
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 84
• Package Type: PLCC
• Memory Type: Flash
• Lead Free Status / RoHS Status: Not Compliant

Document #: 38-03031 Rev. *A
Switching Characteristics
Combinatorial Mode Parameters
t
t
t
t
t
Input Registered/Latched Mode Parameters
t
t
t
t
t
t
Output Registered/Latched Mode Parameters
t
t
t
t
t
t
t
f
f
f
t
37x
Pipelined Mode Parameters
t
f
Notes:
14. All AC parameters are measured with 16 outputs switching and 35-pF AC Test Load.
15. This specification is intended to guarantee interface compatibility of the other members of the CY7C370i family with the CY7C374i. This specification is met for
Parameter
PD
PDL
PDLL
EA
ER
WL
WH
IS
IH
ICO
ICOL
CO
S
H
CO2
SCS
SL
HL
MAX1
MAX2
MAX3
OH
ICS
MAX4
the devices operating at the same ambient temperature and at the same power supply voltage.
–t
IH
Input to Combinatorial Output
Input to Output Through Transparent Input or
Output Latch
Input to Output Through Transparent Input and
Output Latches
Input to Output Enable
Input to Output Disable
Clock or Latch Enable Input LOW Time
Clock or Latch Enable Input HIGH Time
Input Register or Latch Set-Up Time
Input Register or Latch Hold Time
Input Register Clock or Latch Enable to
Combinatorial Output
Input Register Clock or Latch Enable to Output
Through Transparent Output Latch
Clock or Latch Enable to Output
Set-Up Time from Input to Clock or Latch Enable
Register or Latch Data Hold Time
Output Clock or Latch Enable to Output Delay
(Through Memory Array)
Output Clock or Latch Enable to Output Clock
or Latch Enable (Through Memory Array)
Set-Up Time from Input Through Transparent
Latch to Output Register Clock or Latch Enable
Hold Time for Input Through Transparent Latch
from Output Register Clock or Latch Enable
Maximum Frequency with Internal Feedback
(Least of 1/t
Maximum Frequency Data Path in Output
Registered/Latched Mode (Lesser of 1/(t
t
Maximum Frequency with External Feedback
(Lesser of 1/(t
Output Data Stable from Output Clock Minus
Input Register Hold Time for 7C37x
Input Register Clock to Output Register Clock
Maximum Frequency in Pipelined Mode (Least
of 1/(t
or 1/t
WH
), 1/(t
SCS
CO
+ t
S
)
+ t
IS
SCS
), 1/t
[1]
H
CO
), or 1/t
[1]
, 1/(t
Description
ICS
+ t
S
, 1/(t
S
Over the Operating Range
) and 1/(t
[1]
CO
+ t
[1]
WL
)
H
[1]
), or 1/t
+ t
[1]
WH
WL
[1]
), 1/(t
CO
+ t
[1]
[9, 15]
)
WH
[9]
IS
[9]
))
[9]
+ t
WL
IH
+
),
158.3
7C374i–125
Min.
83.3
[14]
125
125
5.5
10
3
3
2
2
0
8
0
0
8
Max.
6.5
10
13
15
14
14
14
16
14
7C374i–100
Min.
76.9
100
143
100
10
12
10
3
3
2
2
6
0
0
0
Max.
12
15
16
16
16
16
18
16
7
7C374iL–83
Min.
67.5
83.3
125
7C374i–83
12
15
83
12
4
4
3
3
8
0
0
0
Max.
15
18
19
19
19
19
21
19
8
7C374iL–66
Min.
66.6
100
7C374i–66
10
50
15
20
66
15
CY7C374i
5
5
4
4
0
0
0
Max.
Page 7 of 15
20
22
24
24
24
24
26
10
24
MHz
MHz
MHz
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns