CY7C341B-35JC Cypress Semiconductor Corp, CY7C341B-35JC Datasheet - Page 6

• Manufacturer Part Number: CY7C341B-35JC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C341B-35JC

• Family Name: MAX®
• # Macrocells: 192
• Number Of Usable Gates: 3750
• Frequency (max): 40MHz
• Propagation Delay Time: 35ns
• Number Of Logic Blocks/elements: 12
• # I/os (max): 64
• Operating Supply Voltage (typ): 5V
• In System Programmable: No
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 84
• Package Type: PLCC
• Memory Type: EPROM
• Lead Free Status / RoHS Status: Not Compliant

Document #: 38-03016 Rev. *C
External Switching Characteristics
Internal Switching Characteristics
t
t
t
t
t
t
t
f
t
t
t
t
t
t
t
f
t
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Notes:
Parameter
PD1
PD2
SU
CO1
H
WH
WL
MAX
ACO1
AS1
AH
AWH
AWL
CNT
ODH
CNT
ACNT
ACNT
IN
IO
EXP
LAD
LAC
OD
ZX
XZ
RSU
RH
LATCH
RD
COMB
IC
ICS
5. The f
6. This parameter is measured with a positive-edge-triggered clock at the register. For negative-edge clocking, the t
7. This parameter is measured with a 16-bit counter programmed into each LAB.
8. C1 = 5 pF.
4. C1 = 35 pF.
Parameter
MAX
values represent the highest frequency for pipeline data.
Dedicated Input to Combinatorial Output Delay
I/O Input to Combinatorial Output Delay
Global Clock Set-up Time
Synchronous Clock Input to Output Delay
Input Hold Time from Synchronous Clock Input
Synchronous Clock Input High Time
Synchronous Clock Input Low Time
Maximum Register Toggle Frequency
Dedicated Asynchronous Clock Input to Output Delay
Dedicated Input or Feedback Set-up Time to
Asynchronous Clock Input
Input Hold Time from Asynchronous Clock Input
Asynchronous Clock Input HIGH Time
Asynchronous Clock Input LOW Time
Minimum Global Clock Period
Output Data Hold Time After Clock
Maximum Internal Global Clock Frequency
Minimum Internal Array Clock Frequency
Maximum Internal Array Clock Frequency
Dedicated Input Pad and Buffer Delay
I/O Input Pad and Buffer Delay
Expander Array Delay
Logic Array Data Delay
Logic Array Control Delay
Output Buffer and Pad Delay
Output Buffer Enable Delay
Output Buffer Disable Delay
Register Set-Up Time Relative to Clock
Signal at Register
Register Hold Time Relative to Clock
Signal at Register
Flow-Through Latch Delay
Register Delay
Transparent Mode Delay
Asynchronous Clock Logic Delay
Synchronous Clock Delay
Description
Description
USE ULTRA37000™ FOR
[4]
[8]
[4]
Over the Operating Range
Over the Operating Range
ALL NEW DESIGNS
[5]
[6]
[6]
[4]
[4]
[7]
[7]
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
[4]
[4]
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Min.
7C341B-25
6
4
Min.
62.5
7C341B-25
15
11
50
50
0
8
8
5
6
9
2
ACH
Max
Max.
12
12
10
10
10
14
and t
5
6
5
3
1
3
3
25
40
14
25
20
20
ACL
parameter must be swapped.
Min.
Min.
12.5
12.5
40.0
33.3
33.3
12
7C341B-35
8
7C341B-35
25
10
10
16
14
0
2
CY7C341B
Max
Max.
Page 6 of 12
11
11
20
14
13
13
13
16
35
55
20
35
30
30
6
4
2
4
1
MHz
MHz
MHz
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns