SAA7144HL/V1,557 Trident Microsystems, Inc., SAA7144HL/V1,557 Datasheet - Page 21

• Manufacturer Part Number: SAA7144HL/V1,557
• Manufacturer: Trident Microsystems, Inc.

Specifications of SAA7144HL/V1,557

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Philips Semiconductors
9397 750 14454
Product data sheet
8.6 Clock generation circuit
8.7 Power-on reset
The internal CGC generates all clock signals required for the video input processor.
The internal signal LFCO is a digital-to-analog converted signal provided by the horizontal
PLL. It is the multiple of the line frequency:
The LFCO signal is multiplied by a factor of 2 and 4 in the internal PLL circuit (including
phase detector, loop filtering, VCO and frequency divider) to obtain the output clock
signals. The rectangular output clocks have a 50 % duty factor.
Table 4:
A missing clock, insufficient digital or analog V
sequence; all outputs are forced to 3-state; see
After sufficient power supply voltage, the outputs LLC and SDA return from 3-state to
active.
Clock
XTAL
LLC
LLC2 (internal)
LLC4 (internal)
LLC8 (virtual)
Fig 18. Block diagram of clock generation circuit.
LFCO
6.75 MHz = 429
6.75 MHz = 432
Clock frequencies
BAND PASS
FC = LLC/4
f
f
H
H
(50 Hz), or
(60 Hz).
Rev. 01 — 21 April 2005
DETECTION
CROSS
ZERO
DETECTION
PHASE
Frequency (MHz)
24.576
27
13.5
6.75
3.375
DDA0
Figure
supply voltages will start the reset
Quadruple video input processor
19.
DIVIDER
FILTER
LOOP
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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LLC
LLC2