STN8815D0A12H11E STMicroelectronics, STN8815D0A12H11E Datasheet - Page 16

• Manufacturer Part Number: STN8815D0A12H11E
• Manufacturer: STMicroelectronics

Specifications of STN8815D0A12H11E

• Lead Free Status / RoHS Status: Supplier Unconfirmed

STn8815A12
2.21
2.22
2.23
2.24
Liquid crystal display controller (LCDC)
This interface drives LCD panels, and supports the following displays:
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The resolution can be set as follows:
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The interface supports frame modulation and directly supports Sharp HR-TFT panels.
Master display interface (MDIF)
This interface drives LCD display modules, that is, panels that include their own display
memory and perform LCD panel refresh themselves. The MDIF is a parallel bidirectional
interface that can send commands or data to or read data from the display panel logic. It has
a DMA engine to automatically fetch data/commands from main memory without CPU
intervention.
In addition, the MDIF includes a submode to drive serial LCD smart panels.
Pulse width light modulator (PWL)
The PWL provides control of LCD backlighting. It produces a series of pulses that are fed to
the backlighting, where the width (or duty cycle) of the pulses determines the perceived
lighting level. An 8-bit random sequence generator decreases the spectral power at the
modulator harmonic frequencies.
General purpose inputs/outputs (GPIOs)
The STn8815A12 provides 124 programmable inputs or outputs that have switchable pull-up
and pull-down resistors and are controllable in two modes:
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The GPIO interface provides the following individually programmable functions.
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STN displays: single- or dual-panel with 8-bit color and 4- or 8-bit monochrome,
TFT displays: 12-, 16-, 18- and 24-bit color.
1-, 2- or 4-bits-per-pixel (bpp) palettized for mono STN,
1-, 2-, 4- or 8-bpp palettized for color STN and TFT,
16-bpp true-color non-palettized for color STN and TFT,
24-bpp packed and non-packed true-color (non-palettized) for color TFT.
Software mode through an APB bus interface,
Hardware mode through a hardware control interface.
Any number of pins may be configured as interrupt sources.
Debouncing logic can be enabled for each GPIO to filter out glitches on I/Os.
Any GPIO may be used to wake up the device from sleep mode independent of
interrupt programming, and the input level that triggers wake-up is definable for each
enabled GPIO.
Architecture overview
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