MC94MX21DVKN3 Freescale, MC94MX21DVKN3 Datasheet

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... This document contains information on a new product. Specifications and information herein are subject to change without notice. © Freescale Semiconductor, Inc., 2005, 2006. All rights reserved. Document Number: MC94MX21 MC94MX21 Package Information (MAPBGA– ...

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... Memory Control Enhanced Multimedia Accelerator (eMMA) Pre- and Post- Processing Video Accelerator MC94MX21 Technical Data, Rev. 1.5 Connectivity CSPI x 3 SSI Audio Mux UART x 4 1-WIRE IrDA USB OTG/ 2 Hosts Memory Expansion MMC/ PCMCIA/CF Memory Interface SDRAMC EIM/BMI NFC Freescale Semiconductor ...

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... The ARM Ltd. documentation is available from http://www.arm.com. 1.4 Ordering Information Table 1 provides ordering information for the device. See supply voltage requirements. Part Order Number MC94MX21DVKN3 289-lead MAPBGA 0.65mm, 14mm x 14mm Freescale Semiconductor Table 4 on page 14 Table 1. Ordering Information Package Size ...

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... General-Purpose I/O (GPIO) Ports — Debug Capability 2 Signal Descriptions Table 2 identifies and describes the i.MX21 signals. Pin assignment is provided in Assignment and Package Information” and in the “Signal Multiplexing Scheme” table within the reference manual MC94MX21 Technical Data, Rev. 1.5 S) Section 4, “Pin Freescale Semiconductor ...

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... To hardwire these inputs low, terminate with a 1 KΩ resister to ground. For a logic high, terminate with a 1 KΩ resistor to VDDA. Do not change the state of these inputs after power-up. Boot 3 should always be tied to logic low. Freescale Semiconductor depends solely upon the user application, however there are a few Table 2. i.MX21 Signal Descriptions ...

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... These are special factory test signals. However, these signals are also multiplexed with GPIO PORT E as well as alternate keypad signals. If not using these signals for GPIO functions or for other multiplexed functions, then configure as GPIO input with pull-up enabled, and leave connect. 6 Function/Notes SDRAM Controller Clocks and Resets MC94MX21 Technical Data, Rev. 1.5 Freescale Semiconductor ...

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... Start signal output for gate driver. This signal is invert version of PS (Sharp panel dedicated signal). This signal is multiplexed with the SLCDC1_RS. REV Signal for common electrode driving signal preparation (Sharp panel dedicated signal). This signal is multiplexed with SLCDC1_D0. Freescale Semiconductor Function/Notes JTAG CMOS Sensor Interface LCD Controller MC94MX21 Technical Data, Rev ...

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... External DMA Request input signal. This signal is multiplexed with CSPI1_RDY. EXT_DMAGRANT External DMA Grant output signal. This signal is multiplexed with LD[16] of LCDC and CSPI1_SS1 of CSPI1. 8 Function/Notes Smart LCD Controller Bus Master Interface (BMI) External DMA MC94MX21 Technical Data, Rev. 1.5 Freescale Semiconductor ...

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... PCMCIA Read Write output signal to control external transceiver direction. Asserted high for read access and negated low for write access. This signal is multiplexed with NFRE signal of NF. PC_PWRON PCMCIA input signal to indicate that the card power has been applied and stabilized. Freescale Semiconductor Function/Notes NAND Flash Controller PCMCIA Controller MC94MX21 Technical Data, Rev ...

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... USB OTG Transceiver ON output signal. This signal is muxed with SLCDC1_DAT9. USBG_FS USB OTG Full Speed output signal. This signal is multiplexed with external transceiver USBG_TXR_INT signal of USB OTG. This signal is muxed with SLCDC1_DAT10. 10 Function/Notes CSPI General Purpose Timers USB On-The-Go MC94MX21 Technical Data, Rev. 1.5 Freescale Semiconductor ...

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... SD Data bidirectional signals. SD2_D[3:2] are multiplexed with SLCDC1_RS and SLCDC_D0 signals from SLCDC1. UART1_RXD Receive Data input signal UART1_TXD Transmit Data output signal UART1_RTS Request to Send input signal UART1_CTS Clear to Send output signal Freescale Semiconductor Function/Notes Secure Digital Interface UARTs – IrDA/Auto-Bauding MC94MX21 Technical Data, Rev. 1.5 Signal Descriptions 11 ...

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... SAP_FS Frame Sync signal which is output in master and input in slave. 2 I2C_CLK I C Clock 2 I2C_DATA I C Data OWIRE 1-Wire input and output signal. This signal is multiplexed with JTAG RTCK. 12 Function/Notes 2 S protocol and AC97 1-Wire MC94MX21 Technical Data, Rev. 1.5 Freescale Semiconductor ...

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... QVDD Power supply pins for silicon internal circuitry QVSS Quiet GND pins for silicon internal circuitry QVDDX Power supply pin for the ARM core. Externally connect directly to QVDD Freescale Semiconductor Function/Notes PWM General Purpose Input/Output Keypad Noisy Supply Pins Supply Pins – Analog Modules Internal Power Supplies MC94MX21 Technical Data, Rev ...

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... QVDD, QVDDx QVDD, QVDDx VDDA MC94MX21 Technical Data, Rev. 1.5 3) may cause 4) is not implied. Min Max Units -0.3 2.1 V -0.3 3 -0.3 VDD + 0 -55 150 C Table 4. Minimum Maximum Unit -30 70 °C 1.70 3.30 V 1.65 1.80 V 1.70 1.80 V 1.70 3.30 V Freescale Semiconductor ...

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... Data labeled Typical is not guaranteed, but is intended as an indication of the IC's potential performance. 2. For DSCR definition refer to the System Control chapter in the reference manual. Table 6 shows the input and output capacitance for the device. Parameter Input capacitance Output capacitance Freescale Semiconductor Table 5. DC Characteristics Symbol Test Conditions Min V – ...

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... MC94MX21 Technical Data, Rev. 1.5 Symbol Typ Max Units 180 – QVDD QVDDX – NVDD1 mA through 6.6 – NVDD6 VDDA I STBY ° – ° – under an operating temperature RMS Maximum Unit 100 ns – – ms Units ns ns Freescale Semiconductor ...

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... Frequency jitter (p-p) Phase jitter (p-p) Integer MF, FPL mode, Vcc=1.7V Power dissipation FOL mode, integer MF, f dck Freescale Semiconductor Table 10. In this table reference clock period after the ref Table 10. DPLL Specifications Test Conditions – ...

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... RESET_POR RESET_DRAM HRESET RESET_OUT CLK32 HCLK Figure 2. Timing Relationship with POR RESET_IN HRESET RESET_OUT 6 CLK32 HCLK Figure 3. Timing Relationship with RESET_IN Exact 300ms 3 5 MC94MX21 Technical Data, Rev. 1.5 Figure 2 and 7 cycles @ CLK32 4 14 cycles @ CLK32 14 cycles @ CLK32 4 Freescale Semiconductor ...

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... Minimum and maximum timings for the External request and External grant signals are present in Table 12. Figure 4 shows the minimum time for which the External Grant signal remains asserted when an External DMA request is de-asserted immediately after sensing grant signal active. Freescale Semiconductor 1.8V ± 0.10V Min Max 800 300 300 ...

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... MC94MX21 Technical Data, Rev. 1.5 t max_write 1.8 V Unit WCS BCS 8 hclk + 7.17 8 hclk + 3. hclk - 17.96 9 hclk - 8. hclk - 5.84 8 hclk - 0. hclk - 15.9 3 hclk - 9.12 ns Freescale Semiconductor ...

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... Note: If the MMD latch data at next rising edge, the ideally max clock can be as much as double, but because the BMI data pads are slow pads and it max frequency can only up to 18MHz, the max clock frequency can only MHz. Freescale Semiconductor 1T ...

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... BMI_CLK/CS out once the BMI_WRITE is changed from low to high. 22 Can be asserted any time RxD1 RxD2 Tds Ts Table 14. MMD Write BMI Timing Symbol Minimum Typical Ts 11 – – Tds 5 – MC94MX21 Technical Data, Rev. 1.5 Last RxD Th Maximum Unit – ns – ns – ns Freescale Semiconductor ...

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... The BMI can latch the data either at falling edge or the next rising edge of the BMI_CLK/CS according to the DATA_LATCH bit. When the DATA_LATCH bit is set, the BMI latch data at the next rising edge and latch the last data using the internal clock. BMI_WRITE signal can not be negated when the WRITE operation is proceeding. Freescale Semiconductor 1T Tdh Tds ...

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... Each rising edge of BMI_CLK/CS will determine if data should be latched to RxFIFO from the data bus. 24 Total has COUNT+1 clocks in one burst Can be asserted any time Can be asserted any time RxD2 RxD1 Tds2 Tds1 Symbol Minimum Typical Tds1 14 – Tds2 14 – MC94MX21 Technical Data, Rev. 1.5 Last RxD Maximum Unit – ns – ns Freescale Semiconductor ...

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... In this master mode operation, Int_Clk is derived from HCLK through an integer divider DIV of BMI control register and it is used to control the read/write cycle timing by generate WRITE and CLK/CS signals. Freescale Semiconductor Ttds Trdh Ttdh TxD ...

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... WAIT signal. So the BMI_WRITE will be asserted at least for 1+WS Int_Clk period. 26 1+ws Last TxD TxD2 BMI write BMI write written to READ bit of control reg1 Figure 12 shows the BMI write timing when the WAIT bit is set. MC94MX21 Technical Data, Rev. 1.5 Figure 11 1+ws 1+ws RxD1 RxD2 Tdh Freescale Semiconductor ...

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... Control Register (PERIODREG2) can also be programmed to a fixed data transfer rate for either CSPI1 or CSPI2. When the CSPI1 module is configured as a slave, the user can configure the SPI 1 Control Register (CONTROLREG1) to match the external CSPI master’s timing. In this configuration, SS Freescale Semiconductor 1+ws 1+ws ...

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... Figure 16. Master CSPI Timing Diagram Ignore SPI_RDY Level Trigger SS (input) SCLK, MOSI, MISO Figure 17. Slave CSPI Timing Diagram FIFO Advanced by BIT COUNT SS (input) 6 SCLK, MOSI, MISO Figure 18. Slave CSPI Timing Diagram FIFO Advanced by SS Rising Edge MC94MX21 Technical Data, Rev. 1.5 Freescale Semiconductor ...

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... When CSTN, TFT or monochrome mode with bus width = 1, SCLK is equal to the pixel clock. When monochrome with other bus width settings, SCLK is equal to the pixel clock divided by bus width. The polarity of SCLK and LD can also be programmed. Maximum frequency of SCLK is HCLK / 3 for TFT and CSTN, otherwise LD output will be incorrect. Freescale Semiconductor Figure 14 through Parameter ...

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... XMAX (0,1) (0,2) (0,X-1) Minimum T5+T6+T7-1 (VWAIT1·T2)+T5+T6+T7-1 – Figure MC94MX21 Technical Data, Rev. 1.5 Display region Line Y T7 Value Unit Ts XMAX+T5+T6+T7 Ts VWIDTH·T2 Ts (VWAIT2·T2)+1 Ts HWIDTH+1 Ts HWAIT2+3 Ts HWAIT1+1 Ts 20, all 3 signals are active low. Figure 20, SCLK is Freescale Semiconductor ...

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... REV toggle delay from last LD of line Note: • Falling of SPL/SPR aligns with first LD of line. • Falling of PS aligns with rising edge of CLS. • REV toggles in every HSYN period. Freescale Semiconductor XMAX Figure 21. Sharp TFT Panel Timing Table 21. Sharp TFT Panel Timing Minimum – ...

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... When monochrome mode with bus width = 2, 4, and and 4 Tpix respectively XMAX Ts Table 22. Non-TFT Mode Panel Timing Minimum 2 1 – 1 MC94MX21 Technical Data, Rev. 1 Value Unit HWAIT2+2 Tpix HWIDTH+1 Tpix ≤ ≤ – HWAIT1+1 Tpix Figure 67, all these 3 signals are Freescale Semiconductor ...

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... RS T2 LCD_CS LCD_CLK (LCD_DATA[6]) SDATA (LCD_DATA[7 LCD_CS LCD_CLK (LCD_DATA[6]) SDATA (LCD_DATA[7]) RS Figure 23. SLCDC Serial Transfer Timing Freescale Semiconductor T1 T4 MSB T6 RS=0 ≥ command data, RS=1≥ display data SCKPOL = 1, CSPOL = MSB T6 RS=0 ≥ command data, RS=1≥ display data SCKPOL = 0, CSPOL = 0 ...

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... Register select setup time T5 Register select hold time 34 Minimum command data display data CSPOL = command data display data CSPOL = 1 Minimum MC94MX21 Technical Data, Rev. 1.5 Maximum Unit 962 ns – ns – ns – ns – ns – ns – ns Maximum Unit 962 ns – ns – ns – ns – ns Freescale Semiconductor ...

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... Output hold time 3 —10/30 cards 6b Output setup time 3 7 Output delay time ≤ 100 pF / 250 pF (10/30 cards) L ≤ 250 pF (21 cards) L ≤ card) L Freescale Semiconductor Valid Data 7 Valid Data 6a 1.8 V ± 0.1 V Min 1 —10/30 cards 6/33 15/75 – 10/50 (5.00) – ...

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... Figure 26 Symbol S Data bits cycles CRC ****** Identification Timing N cycles CRC ****** MC94MX21 Technical Data, Rev. 1.5 Figure 26 through through Figure 30 Host Active Definition Start bit (0) Transmitter bit (Host = 1, Card = 0) One-cycle pull-up (1) End bit (1) CID/OCR Content CID/OCR Content SET_RCA Timing and Freescale Semiconductor ...

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... SD_CMD lines as usual. Data transmission from the card starts after the access time delay N from the last bit of the read command. If the system is in multiple block read mode, the card sends a continuous flow of data blocks with distance N data stops two clock cycles after the end bit of the stop command. Freescale Semiconductor N cycles CR ...

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... Timing of single block read N cycles CR Response CRC E Z ****** Content ****** ***** Read Data N cycles AC N cycles CR Response Content CRC ****** Content ***** Timing of stop command (CMD12, data transfer mode) MC94MX21 Technical Data, Rev. 1.5 CRC E Z ***** ***** ***** Read Data N cycles AC Timing of multiple block read CRC E Z ***** Freescale Semiconductor ...

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... Figure 29. Timing Diagrams at Data Write The stop transmission command may occur when the card is in different states. different scenarios on the bus. Freescale Semiconductor MC94MX21 Technical Data, Rev. 1.5 Specifications Figure 30 shows the 39 ...

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... MMC/SD bus clock, CLK (All values are referred to minimum (VIH) and maximum (VIL) Command response cycle Identification response cycle Access time delay cycle 40 Figure 26 through Symbol Minimum NCR 2 NID 5 NAC 2 MC94MX21 Technical Data, Rev. 1.5 Figure 30 Maximum Unit 64 Clock cycles 5 Clock cycles TAAC + NSAC Clock cycles Freescale Semiconductor ...

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... CMD ****** DAT[1] S Block Data For 4-bit DAT[2] Block Data For 4-bit Figure 32. SDIO ReadWait Timing Diagram Freescale Semiconductor Figure 26 through Figure 30 Symbol Minimum NRC 8 NCC 8 NWR 2 NST ...

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... NFALE NFIO[7:0] Figure 33. Command Latch Cycle Timing DIagram 42 Figure 36 depict the relative timing requirements among different Table 28 lists the timing parameters. The NAND Flash Controller NF1 NF2 NF3 NF4 NF5 NF6 NF7 NF9 NF8 command MC94MX21 Technical Data, Rev. 1. Freescale Semiconductor ...

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... NFWE NF6 NFALE NFIO[15:0] Figure 35. Write Data Latch Timing DIagram NFCLE NFCE NFRE NFRB NFIO[15:0] Figure 36. Read Data Latch Timing Diagram Freescale Semiconductor NF4 NF5 NF7 NF8 NF9 Address Time it takes for SW to issue the next address command NF10 NF11 NF5 ...

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... Unit Max Min Max – 30 – ns – 30 – ns – 30 – ns – 30 – ns – 30 – ns – 30 – ns – 30 – ns – 30 – ns – 30 – ns – 60 – ns – 30 – ns – 120 – ns – 45 – ns – 60 – ns – 15 – ns – 15 – ns – 0 – ns Freescale Semiconductor ...

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... Table 29. PWM Output Timing Parameters Ref No. Parameter 1 System CLK frequency 2a Clock high time 2b Clock low time 3a Clock fall time 3b Clock rise time 4a Output delay time 4b Output setup time Freescale Semiconductor 1.8 V ± 0.1 V Minimum Maximum Minimum 0 45 12.29 – 9.91 – – ...

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... Note: CKE is high during the read/write cycle. 1.8 V ± 0.1 V Minimum Maximum 3.00 3.00 7.5 4.78 3.03 MC94MX21 Technical Data, Rev 3.0 V ± 0.3 V Unit Minimum Maximum – 3 – ns – 3 – ns – 7.5 – ns – 3 – ns – 2 – ns Freescale Semiconductor ...

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... SDRAM clock cycle time. The t RCD SDCLK RAS CAS ADDR / BA DQ DQM Figure 39. SDRAM Write Cycle Timing Diagram Freescale Semiconductor 1.8 V ± 0.1 V Minimum Maximum 3.67 2.95 – – – 2 – – – RCD setting can be found in the i.MX21 reference manual. ...

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... – RCD 3.41 – 2.45 – MC94MX21 Technical Data, Rev. 1. 3.0 V ± 0.3 V Unit Minimum Maximum 3 – – ns 7.5 – – – – – ns RCD 2 – – ROW/BA Freescale Semiconductor ...

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... SDRAM clock cycle time. These settings can be found in the i.MX21 reference manual SDCLK CS RAS CAS WE ADDR BA DQ DQM CKE Figure 41. SDRAM Self-Refresh Cycle Timing Diagram Freescale Semiconductor 1.8 V ± 0.1 V Minimum Maximum 3.00 – 3.00 – 7.5 – 3.67 – 2.95 – ...

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... The SSI can be connected to 4 set of ports, SAP, SSI1, SSI2 and SSI3. CK Output FS (bl) Output FS (wl) Output STXD Output SRXD Input Note: SRXD input in synchronous mode only. Figure 42. SSI Transmitter Internal Clock Timing Diagram 50 45 MC94MX21 Technical Data, Rev Freescale Semiconductor ...

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... Figure 43. SSI Receiver Internal Clock Timing Diagram CK Input FS (bl) Input FS (wl) Input STXD Output SRXD Input Note: SRXD Input in Synchronous mode only Figure 44. SSI Transmitter External Clock Timing Diagram CK Input FS (bl) Input FS (wl) Input SRXD Input Figure 45. SSI Receiver External Clock Timing Diagram Freescale Semiconductor ...

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... Freescale Semiconductor ...

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... SRXD hold time after (Rx) CK low 1 15 (Tx/Rx) CK clock period 16 (Tx/Rx) CK clock high period 17 (Tx/Rx) CK clock low period 18 (Tx) CK high to FS (bl) high 19 (Rx) CK high to FS (bl) high Freescale Semiconductor 1.8 V ± 0.1 V Minimum Maximum 23.00 – 0 – 1.20 – 0 – 1.8 V ± 0.1 V ...

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... V ± 0.3 V Unit Minimum Maximum 90.91 – ns 0.01 0.15 ns -0.21 0.05 ns 0.01 0.15 ns -0.21 0.05 ns 0.01 0.15 ns -0.21 0.05 ns 0.01 0.15 ns -0.21 0.05 ns 0.34 0.72 ns Freescale Semiconductor ...

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... All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures. Freescale Semiconductor 1.8 V ± 0.1 V Minimum Maximum 0 ...

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... Freescale Semiconductor ...

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... When the presence pulse is detected, this bit will be cleared. The presence pulse is used by the bus master to determine if at least one DS2502 is connected. Software will determine if more than one DS2502 exists. The one-wire will sample for the DS2502 presence pulse. The presence pulse is latched in the one-wire Freescale Semiconductor 1.8 V ± 0.1 V Minimum Maximum 9 ...

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... After a Read, the control register RDST bit is set to the value of the read. 58 AutoClear WR0 Set WR0 Write 0 Slot 128us 17us 100us Figure 47. Write 0 Timing Auto Clear WR1/R Set WR1/RD Write “1” Slot 117us 5us Figure 48. Write 1 Timing MC94MX21 Technical Data, Rev. 1. Freescale Semiconductor ...

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... This shows that the user should take care of the main clock frequency when using the one-wire module. If the main clock is an exact integer multiple of 1 MHz, then the generated frequency will be exactly 1 MHz. A main clock frequency below 10 MHz might cause a misbehavior of the module. Freescale Semiconductor Auto Clear WR1/RD Set WR1/RD Read “0” Slot 117us ...

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... TXDM_ OEB SE0 interval of EOP FEOPT Data transfer rate PERIOD PERIOD 2 Parameter MC94MX21 Technical Data, Rev TXDM_OEB 3 t TXDP_OEB t FEOPT 5 3.0 V ± 0.3 V Unit Minimum Maximum 83.14 83.47 ns 81.55 81.98 ns 83.54 83.8 ns 248.9 249.13 ns 160 175 ns 11.97 12.03 Mb/s Freescale Semiconductor ...

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... Ref No. Parameter 1 Hold time (repeated) START condition 2 Data hold time 3 Data setup time 4 HIGH period of the SCL clock 5 LOW period of the SCL clock 6 Setup time for STOP condition Freescale Semiconductor Minimum Minimum 188 0 88 500 500 185 MC94MX21 Technical Data, Rev. 1. ...

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... EB (falling edge) LBA (negated falling edge) LBA (negated rising edge) Burst Clock (rising edge) Burst Clock (falling edge) Read Data Write Data (negated falling) Write Data (negated rising) DTACK 10a Figure 53. EIM Bus Timing Diagram MC94MX21 Technical Data, Rev 10a Freescale Semiconductor ...

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... Write Data Invalid 10a DTACK setup time 11 Burst Clock (BCLK) cycle time 1. Clock refers to the system clock signal, HCLK, generated from the System DPLL Freescale Semiconductor Table 42. EIM Bus Timing Parameters 1.8 V ± 0.1 V 3.0 V ± 0.3 V Min Typical 3.97 6 ...

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... Note: Signals listed with lower case letters are internal to the device. hclk hselm_weim_cs[0] htrans Seq/Nonseq hwrite haddr hready weim_hrdata weim_hready BCLK A[24:0] Last Valid Address CS[0] R/W LBA OE EB (EBC=0) EB (EBC=1) DATA_IN 64 Read V1 Last Valid Data Read Figure 54. WSC = 1, A.HALF/E.HALF MC94MX21 Technical Data, Rev Freescale Semiconductor ...

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... Last Valid Data weim_hrdata weim_hready BCLK A[24:0] Last Valid Address CS[0] R/W LBA OE EB D[31:0] Last Valid Data Figure 55. WSC = 1, WEA = 1, WEN = 1, A.HALF/E.HALF Freescale Semiconductor Write Data (V1) Last Valid Data Write MC94MX21 Technical Data, Rev. 1. Specifications Unknown V1 Write Data (V1) 65 ...

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... Read haddr V1 hready weim_hrdata Last Valid Data weim_hready BCLK A[24:0] Last Valid Addr CS[0] R/W LBA OE EB (EBC=0) EB (EBC=1) DATA_IN Figure 56. WSC = 1, OEA = 1, A.WORD/E.HALF 66 Address V1 Read 1/2 Half Word MC94MX21 Technical Data, Rev Word Address 2/2 Half Word Freescale Semiconductor ...

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... Last Valid Data weim_hrdata weim_hready BCLK A[24:0] Last Valid Addr CS[0] R/W LBA OE EB D[31:0] Figure 57. WSC = 1, WEA = 1, WEN = 1, A.WORD/E.HALF Freescale Semiconductor Write Data (V1 Word) Last Valid Data Address V1 1/2 Half Word MC94MX21 Technical Data, Rev. 1. Specifications Address Write 2/2 Half Word 67 ...

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... Read haddr V1 hready weim_hrdata weim_hready BCLK A[24:0] Last Valid Addr CS[3] R/W LBA OE EB (EBC=0) EB (EBC=1) DATA_IN Figure 58. WSC = 3, OEA = 2, A.WORD/E.HALF 68 Last Valid Data Address V1 Read 1/2 Half Word MC94MX21 Technical Data, Rev Word Address 2/2 Half Word Freescale Semiconductor ...

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... BCLK A[24:0] Last Valid Addr CS[3] R/W LBA OE EB D[31:0] Last Valid Data Figure 59. WSC = 3, WEA = 1, WEN = 3, A.WORD/E.HALF Freescale Semiconductor Write Data (V1 Word) Last Valid Data Address V1 Write 1/2 Half Word MC94MX21 Technical Data, Rev. 1. Specifications Address 2/2 Half Word 69 ...

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... Read haddr V1 hready weim_hrdata weim_hready BCLK A[24:0] Last Valid Addr CS[2] R/W LBA OE EB (EBC=0) EB (EBC=1) DATA_IN Figure 60. WSC = 3, OEA = 4, A.WORD/E.HALF 70 Last Valid Data Address V1 Read 1/2 Half Word MC94MX21 Technical Data, Rev Word Address 2/2 Half Word Freescale Semiconductor ...

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... BCLK A[24:0] Last Valid Addr CS[2] R/W LBA OE EB D[31:0] Last Valid Data Figure 61. WSC = 3, WEA = 2, WEN = 3, A.WORD/E.HALF Freescale Semiconductor Write Data (V1 Word) Last Valid Data Address V1 Write 1/2 Half Word MC94MX21 Technical Data, Rev. 1. Specifications Address 2/2 Half Word 71 ...

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... Read haddr V1 hready weim_hrdata Last Valid Data weim_hready BCLK A[24:0] Last Valid Addr CS[2] R/W LBA OE EB (EBC=0) EB (EBC=1) DATA_IN Figure 62. WSC = 3, OEN = 2, A.WORD/E.HALF 72 Address V1 Read 1/2 Half Word MC94MX21 Technical Data, Rev Word Address 2/2 Half Word Freescale Semiconductor ...

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... V1 hready weim_hrdata weim_hready BCLK Last Valid Addr A[24:0] CS[2] R/W LBA OE EB (EBC=0) EB (EBC=1) DATA_IN Figure 63. WSC = 3, OEA = 2, OEN = 2, A.WORD/E.HALF Freescale Semiconductor Last Valid Data Address V1 Read 1/2 Half Word MC94MX21 Technical Data, Rev. 1. Specifications V1 Word Address 2/2 Half Word 73 ...

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... BCLK A[24:0] Last Valid Addr CS[2] R/W LBA OE EB D[31:0] Last Valid Data Figure 64. WSC = 2, WWS = 1, WEA = 1, WEN = 2, A.WORD/E.HALF 74 Write Data (V1 Word) Last Valid Data Address V1 Write 1/2 Half Word MC94MX21 Technical Data, Rev. 1. Unknown Address 2/2 Half Word Freescale Semiconductor ...

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... A[24:0] Last Valid Addr CS[2] R/W LBA OE EB D[31:0] Last Valid Data Figure 65. WSC = 1, WWS = 2, WEA = 1, WEN = 2, A.WORD/E.HALF Freescale Semiconductor Write Data (V1 Word) Last Valid Data Address V1 Write 1/2 Half Word MC94MX21 Technical Data, Rev. 1. Specifications Unknown Address 2/2 Half Word ...

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... Last Valid Addr CS[2] R/W LBA OE EB (EBC=0) EB (EBC=1) DATA_IN D[31:0] Figure 66. WSC = 2, WWS = 2, WEA = 1, WEN = 2, A.HALF/E.HALF 76 Nonseq Write V8 Last Valid Data Address V1 Read Read Data Last Valid Data MC94MX21 Technical Data, Rev. 1. Write Data Read Data Address V8 Write Write Data Freescale Semiconductor ...

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... BCLK A[24:0] Last Valid Addr CS[2] R/W LBA OE EB (EBC=0) EB (EBC=1) DATA_IN D[31:0] Figure 67. WSC = 2, WWS = 1, WEA = 1, WEN = 2, EDC = 1, A.HALF/E.HALF Freescale Semiconductor Read Idle Nonseq Write V8 Last Valid Data Address V1 Read Read Data Last Valid Data MC94MX21 Technical Data, Rev. 1. Specifications ...

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... Last Valid Addr CS[3:0] R/W LBA OE EB D[31:0] Last Valid Data Figure 68. WSC = 2, CSA = 1, WWS = 1, A.WORD/E.HALF 78 Write Data (Word) Last Valid Data Address V1 Write Write Data (1/2 Half Word) MC94MX21 Technical Data, Rev. 1. Address Write Data (2/2 Half Word) Freescale Semiconductor ...

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... BCLK A[24:0] Last Valid Addr CS[4] R/W LBA OE EB (EBC=0) EB (EBC=1) DATA_IN D[31:0] Figure 69. WSC = 3, CSA = 1, A.HALF/E.HALF Freescale Semiconductor Nonseq Write V8 Last Valid Data Last Valid Data Address V1 Read Read Data Last Valid Data MC94MX21 Technical Data, Rev. 1. Specifications Write Data ...

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... Last Valid Data weim_hready BCLK A[24:0] Last Valid Addr CS[4] R/W LBA OE EB (EBC=0) EB (EBC=1) DATA_IN Figure 70. WSC = 2, OEA = 2, CNC = 3, BCM = 1, A.HALF/E.HALF 80 Idle Seq Read V2 Read Data (V1) Address V1 CNC Read Read Data (V1) MC94MX21 Technical Data, Rev. 1. Read Data (V2) Address V2 Read Data (V2) Freescale Semiconductor ...

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... BCLK A[24:0] Last Valid Addr CS[4] R/W LBA OE EB (EBC=0) EB (EBC=1) DATA_IN D[31:0] Figure 71. WSC = 2, OEA = 2, WEA = 1, WEN = 2, CNC = 3, A.HALF/E.HALF Freescale Semiconductor Idle Nonseq Write V8 Last Valid Data Read Data Address V1 CNC Read Read Data Last Valid Data MC94MX21 Technical Data, Rev. 1. ...

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... Nonseq hwrite Read haddr V1 hready weim_hrdata weim_hready BCLK A[24:0] Last Valid Addr CS[2] R/W LBA OE EB (EBC=0) EB (EBC=1) ECB DATA_IN Figure 72. WSC = 3, SYNC = 1, A.HALF/E.HALF 82 Nonseq Read V5 Address V1 Read V1 Word V2 Word MC94MX21 Technical Data, Rev. 1. Idle Address V5 V5 Word V6 Word Freescale Semiconductor ...

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... Last Valid Data weim_hready BCLK A[24:0] Last Valid Addr CS[2] R/W LBA OE EB (EBC=0) EB (EBC=1) ECB DATA_IN Figure 73. WSC = 2, SYNC = 1, DOL = [1/0], A.WORD/E.WORD Freescale Semiconductor Seq Seq Read Read Word V2 Word Address V1 Read V1 Word V2 Word V3 Word MC94MX21 Technical Data, Rev. 1. ...

Page 84

... Last Valid Data weim_hready BCLK A[24:0] Last Valid Addr CS[2] R/W LBA OE EB (EBC=0) EB (EBC=1) ECB DATA_IN Figure 74. WSC = 2, SYNC = 1, DOL = [1/0], A.WORD/E.HALF 84 Seq Read V2 V1 Word Address V1 Read V1 1/2 V1 2/2 MC94MX21 Technical Data, Rev. 1. Idle V2 Word Address V2 V2 1/2 V2 2/2 Freescale Semiconductor ...

Page 85

... BCLK Last Valid A[24:0] Addr CS[2] R/W LBA OE EB (EBC=0) EB (EBC=1) ECB DATA_IN Figure 75. WSC = 7, OEA = 8, SYNC = 1, DOL = 1, BCD = 1, BCS = 2, A.WORD/E.HALF Freescale Semiconductor Seq Read Last Valid Data Address V1 Read V1 1/2 V1 2/2 MC94MX21 Technical Data, Rev. 1. Specifications Idle V2 V1 Word V2 Word ...

Page 86

... Last Valid A[24:0] Addr CS[2] R/W LBA OE EB (EBC=0) EB (EBC=1) ECB DATA_IN Figure 76. WSC = 7, OEA = 8, SYNC = 1, DOL = 1, BCD = 1, BCS = 1, A.WORD/E.HALF 86 Seq Read Last Valid Data Address V1 Read V1 1/2 V1 2/2 MC94MX21 Technical Data, Rev. 1. Idle V2 V1 Word V2 Word V2 1/2 V2 2/2 Freescale Semiconductor ...

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... Other bits such as DSZ, OEA, OEN, and so on, may be set according to system and timing requirements of the external device. The waveforms in the following section provide examples of the DTACK signal operation. Freescale Semiconductor Specifications” for more information on how to generate MC94MX21 Technical Data, Rev. 1. ...

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... DTACK Example Waveforms: Internal ARM AHB Word Accesses to Word-Width (32-bit) Memory HCLK BCLK Last Valid ADDR Addr CS[5] RW LBA OE EB (EBC=0) EB (EBC=1) DTACK DATA_IN Figure 77. DTACK Edge Triggered Read Access, WSC=3F, OEA=8, OEN=5, AGE= Read MC94MX21 Technical Data, Rev Data Freescale Semiconductor ...

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... ADDR Last Valid Addr CS[0] RW LBA OE EB (EBC=0) EB (EBC=1) DTACK DATA_IN Figure 78. DTACK Level Sensitive Sequential Read Accesses, WSC=2, EW=1, DCT=1, AGE=0 (Example of Freescale Semiconductor Address V1 Read DCT V1 Word DTACK Remaining High) MC94MX21 Technical Data, Rev. 1. Specifications V1+8 V1+4 V1+4 Word ...

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... Last Valid Addr ADDR CS[0] RWA RW LBA OE EB DTACK DATA_OUT Figure 79. DTACK Level Sensitive Sequential Write Accesses, WSC=2, EW=1, RWA=1, RWN=1, DCT=1, 90 Address V1 RWN Write DCT V1 Word AGE=0 (Example of DTACK Asserting) MC94MX21 Technical Data, Rev. 1. V1+4 V1+8 V1+4 Word V1+8 Freescale Semiconductor ...

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... CSI is programmed to received data on the positive edge. when the CMOS sensor output data is configured for positive edge and the CSI is programmed to received data in negative edge. The parameters for the timing diagrams are listed in calculating the pixel clock rise and fall time is located in Fall Time.” Freescale Semiconductor Table 43 ...

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... HCLK = AHB System Clock Period for HCLK, T HCLK Valid Data Valid Data Valid Data Valid Data 3 4 Parameter Minimum HCLK HCLK T HCLK 0 = Period of CSI_PIXCLK P MC94MX21 Technical Data, Rev Valid Data 6 Valid Data Maximum Unit – / – ns – ns – ns – ns HCLK / 2 MHz Freescale Semiconductor ...

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... Fall Time.” VSYNC PIXCLK DATA[7:0] Figure 83. Sensor Output Data on Pixel Clock Falling Edge CSI Latches Data on Pixel Clock Rising Edge Freescale Semiconductor Figure 84 Section 3.22.3, “Calculation of Pixel Clock Rise Valid Data Valid Data 2 3 MC94MX21 Technical Data, Rev ...

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... Valid Data Valid Data 2 3 Parameter Minimum HCLK HCLK T HCLK 0 = Period of HCLK HCLK MC94MX21 Technical Data, Rev Valid Data 1 Maximum Unit – ns – ns – ns – ns – ns HCLK / 2 MHz Freescale Semiconductor ...

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Pin Assignment and Package Information OE_ A LD9 LD12 LD14 REV HSYNC SD2_D2 ACD CON B LD7 LD5 LD11 LD16 PS SD2_D0 TRAST C LD1 LD3 LD6 LD10 LD17 VSYNC SD2_D3 D ...

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... Pin Assignment and Package Information 4.1 MAPBGA Package Dimensions Figure 85 illustrates the MAPBGA 14 mm × × 1.41 mm package, which has 0.65 mm ball pitch. Figure 85. i.MX21 MAPBGA Mechanical Drawing 96 MC94MX21 Technical Data, Rev. 1. Freescale Semiconductor ...

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... Document Revision History Rev 1.4 is the initial public release of this document. In Rev 1.5, updated Table 29, "PWM Output Timing Parameters." Freescale Semiconductor MC94MX21 Technical Data, Rev. 1. Document Revision History 97 ...

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... Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use ...